tlb.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010 Freescale Semiconductor, Inc.
  4. * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  5. * Timur Tabi <timur@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <asm/mmu.h>
  9. struct fsl_e_tlb_entry tlb_table[] = {
  10. /* TLB 0 - for temp stack in cache */
  11. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  12. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  13. 0, 0, BOOKE_PAGESZ_4K, 0),
  14. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  15. CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  16. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  17. 0, 0, BOOKE_PAGESZ_4K, 0),
  18. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  19. CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  20. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  21. 0, 0, BOOKE_PAGESZ_4K, 0),
  22. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  23. CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  24. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  25. 0, 0, BOOKE_PAGESZ_4K, 0),
  26. /* TLB 1 */
  27. /* *I*** - Covers boot page */
  28. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  29. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
  30. 0, 0, BOOKE_PAGESZ_4K, 1),
  31. /* *I*G* - CCSRBAR */
  32. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  33. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  34. 0, 1, BOOKE_PAGESZ_1M, 1),
  35. /* *I*G* - eLBC */
  36. SET_TLB_ENTRY(1, CONFIG_SYS_ELBC_BASE, CONFIG_SYS_ELBC_BASE_PHYS,
  37. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  38. 0, 2, BOOKE_PAGESZ_1M, 1),
  39. #if defined(CONFIG_TRAILBLAZER)
  40. /* *I*G - L2SRAM */
  41. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
  42. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  43. 0, 9, BOOKE_PAGESZ_256K, 1),
  44. #else
  45. /* *I*G* - PCI */
  46. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  47. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  48. 0, 3, BOOKE_PAGESZ_256M, 1),
  49. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
  50. CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
  51. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  52. 0, 4, BOOKE_PAGESZ_256M, 1),
  53. /* *I*G* - PCI I/O */
  54. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  55. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  56. 0, 5, BOOKE_PAGESZ_256K, 1),
  57. #ifdef CONFIG_SYS_RAMBOOT
  58. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  59. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  60. 0, 6, BOOKE_PAGESZ_1G, 1),
  61. #endif
  62. #endif
  63. };
  64. int num_tlb_entries = ARRAY_SIZE(tlb_table);