controlcenterd.c 9.7 KB

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  1. /*
  2. * (C) Copyright 2013
  3. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <command.h>
  25. #include <env.h>
  26. #include <image.h>
  27. #include <init.h>
  28. #include <net.h>
  29. #include <pci.h>
  30. #include <asm/processor.h>
  31. #include <asm/mmu.h>
  32. #include <asm/cache.h>
  33. #include <asm/immap_85xx.h>
  34. #include <asm/fsl_pci.h>
  35. #include <fsl_ddr_sdram.h>
  36. #include <asm/fsl_serdes.h>
  37. #include <asm/io.h>
  38. #include <linux/delay.h>
  39. #include <linux/libfdt.h>
  40. #include <fdt_support.h>
  41. #include <fsl_mdio.h>
  42. #include <tsec.h>
  43. #include <asm/fsl_law.h>
  44. #include <netdev.h>
  45. #include <i2c.h>
  46. #include <pca9698.h>
  47. #include <watchdog.h>
  48. #include "../common/dp501.h"
  49. #include "controlcenterd-id.h"
  50. enum {
  51. HWVER_100 = 0,
  52. HWVER_110 = 1,
  53. HWVER_120 = 2,
  54. };
  55. struct ihs_fpga {
  56. u32 reflection_low; /* 0x0000 */
  57. u32 versions; /* 0x0004 */
  58. u32 fpga_version; /* 0x0008 */
  59. u32 fpga_features; /* 0x000c */
  60. u32 reserved[4]; /* 0x0010 */
  61. u32 control; /* 0x0020 */
  62. };
  63. #ifndef CONFIG_TRAILBLAZER
  64. static struct pci_device_id hydra_supported[] = {
  65. { 0x6d5e, 0xcdc0 },
  66. {}
  67. };
  68. static void hydra_initialize(void);
  69. #endif
  70. int board_early_init_f(void)
  71. {
  72. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  73. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
  74. /* Reset eLBC_DIU and SPI_eLBC in case we are booting from SD */
  75. clrsetbits_be32(&gur->pmuxcr, 0x00600000, 0x80000000);
  76. /* Set pmuxcr to allow both i2c1 and i2c2 */
  77. setbits_be32(&gur->pmuxcr, 0x00001000);
  78. /* Set pmuxcr to enable GPIO 3_11-3_13 */
  79. setbits_be32(&gur->pmuxcr, 0x00000010);
  80. /* Set pmuxcr to enable GPIO 2_31,3_9+10 */
  81. setbits_be32(&gur->pmuxcr, 0x00000020);
  82. /* Set pmuxcr to enable GPIO 2_28-2_30 */
  83. setbits_be32(&gur->pmuxcr, 0x000000c0);
  84. /* Set pmuxcr to enable GPIO 3_20-3_22 */
  85. setbits_be32(&gur->pmuxcr2, 0x03000000);
  86. /* Set pmuxcr to enable IRQ0-2 */
  87. clrbits_be32(&gur->pmuxcr, 0x00000300);
  88. /* Set pmuxcr to disable IRQ3-11 */
  89. setbits_be32(&gur->pmuxcr, 0x000000F0);
  90. /* Read back the register to synchronize the write. */
  91. in_be32(&gur->pmuxcr);
  92. /* Set the pin muxing to enable ETSEC2. */
  93. clrbits_be32(&gur->pmuxcr2, 0x001F8000);
  94. #ifdef CONFIG_TRAILBLAZER
  95. /*
  96. * GPIO3_10 SPERRTRIGGER
  97. */
  98. setbits_be32(&pgpio->gpdir, 0x00200000);
  99. clrbits_be32(&pgpio->gpdat, 0x00200000);
  100. udelay(100);
  101. setbits_be32(&pgpio->gpdat, 0x00200000);
  102. udelay(100);
  103. clrbits_be32(&pgpio->gpdat, 0x00200000);
  104. #endif
  105. /*
  106. * GPIO3_11 CPU-TO-FPGA-RESET#
  107. */
  108. setbits_be32(&pgpio->gpdir, 0x00100000);
  109. clrbits_be32(&pgpio->gpdat, 0x00100000);
  110. /*
  111. * GPIO3_21 CPU-STATUS-WATCHDOG-TRIGGER#
  112. */
  113. setbits_be32(&pgpio->gpdir, 0x00000400);
  114. return 0;
  115. }
  116. int checkboard(void)
  117. {
  118. printf("Board: ControlCenter DIGITAL\n");
  119. return 0;
  120. }
  121. int misc_init_r(void)
  122. {
  123. return 0;
  124. }
  125. /*
  126. * A list of PCI and SATA slots
  127. */
  128. enum slot_id {
  129. SLOT_PCIE1 = 1,
  130. SLOT_PCIE2,
  131. SLOT_PCIE3,
  132. SLOT_PCIE4,
  133. SLOT_PCIE5,
  134. SLOT_SATA1,
  135. SLOT_SATA2
  136. };
  137. /*
  138. * This array maps the slot identifiers to their names on the P1022DS board.
  139. */
  140. static const char * const slot_names[] = {
  141. [SLOT_PCIE1] = "Slot 1",
  142. [SLOT_PCIE2] = "Slot 2",
  143. [SLOT_PCIE3] = "Slot 3",
  144. [SLOT_PCIE4] = "Slot 4",
  145. [SLOT_PCIE5] = "Mini-PCIe",
  146. [SLOT_SATA1] = "SATA 1",
  147. [SLOT_SATA2] = "SATA 2",
  148. };
  149. /*
  150. * This array maps a given SERDES configuration and SERDES device to the PCI or
  151. * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
  152. */
  153. static u8 serdes_dev_slot[][SATA2 + 1] = {
  154. [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
  155. [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  156. [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
  157. [PCIE2] = SLOT_PCIE5 },
  158. [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
  159. [PCIE2] = SLOT_PCIE3,
  160. [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  161. [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
  162. [PCIE2] = SLOT_PCIE3 },
  163. [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
  164. [PCIE2] = SLOT_PCIE3,
  165. [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  166. [0x1c] = { [PCIE1] = SLOT_PCIE1,
  167. [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  168. [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
  169. [0x1f] = { [PCIE1] = SLOT_PCIE1 },
  170. };
  171. /*
  172. * Returns the name of the slot to which the PCIe or SATA controller is
  173. * connected
  174. */
  175. const char *board_serdes_name(enum srds_prtcl device)
  176. {
  177. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  178. u32 pordevsr = in_be32(&gur->pordevsr);
  179. unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  180. MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  181. enum slot_id slot = serdes_dev_slot[srds_cfg][device];
  182. const char *name = slot_names[slot];
  183. if (name)
  184. return name;
  185. else
  186. return "Nothing";
  187. }
  188. void hw_watchdog_reset(void)
  189. {
  190. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
  191. clrbits_be32(&pgpio->gpdat, 0x00000400);
  192. setbits_be32(&pgpio->gpdat, 0x00000400);
  193. }
  194. #ifdef CONFIG_TRAILBLAZER
  195. int do_bootd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  196. {
  197. return run_command(env_get("bootcmd"), flag);
  198. }
  199. int board_early_init_r(void)
  200. {
  201. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
  202. /*
  203. * GPIO3_12 PPC_SYSTEMREADY#
  204. */
  205. setbits_be32(&pgpio->gpdir, 0x00080000);
  206. setbits_be32(&pgpio->gpodr, 0x00080000);
  207. clrbits_be32(&pgpio->gpdat, 0x00080000);
  208. return ccdm_compute_self_hash();
  209. }
  210. int last_stage_init(void)
  211. {
  212. startup_ccdm_id_module();
  213. return 0;
  214. }
  215. #else
  216. void pci_init_board(void)
  217. {
  218. fsl_pcie_init_board(0);
  219. hydra_initialize();
  220. }
  221. int board_early_init_r(void)
  222. {
  223. unsigned int k = 0;
  224. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
  225. /* wait for FPGA configuration to finish */
  226. while (!pca9698_get_value(0x22, 11) && (k++ < 30))
  227. udelay(100000);
  228. if (k > 30) {
  229. puts("FPGA configuration timed out.\n");
  230. } else {
  231. /* clear FPGA reset */
  232. udelay(1000);
  233. setbits_be32(&pgpio->gpdat, 0x00100000);
  234. }
  235. /* give time for PCIe link training */
  236. udelay(100000);
  237. /*
  238. * GPIO3_12 PPC_SYSTEMREADY#
  239. */
  240. setbits_be32(&pgpio->gpdir, 0x00080000);
  241. setbits_be32(&pgpio->gpodr, 0x00080000);
  242. clrbits_be32(&pgpio->gpdat, 0x00080000);
  243. return 0;
  244. }
  245. int last_stage_init(void)
  246. {
  247. /* Turn on Parade DP501 */
  248. pca9698_direction_output(0x22, 7, 1);
  249. udelay(500000);
  250. dp501_powerup(0x08);
  251. startup_ccdm_id_module();
  252. return 0;
  253. }
  254. /*
  255. * Initialize on-board and/or PCI Ethernet devices
  256. *
  257. * Returns:
  258. * <0, error
  259. * 0, no ethernet devices found
  260. * >0, number of ethernet devices initialized
  261. */
  262. int board_eth_init(struct bd_info *bis)
  263. {
  264. struct fsl_pq_mdio_info mdio_info;
  265. struct tsec_info_struct tsec_info[2];
  266. unsigned int num = 0;
  267. #ifdef CONFIG_TSEC1
  268. SET_STD_TSEC_INFO(tsec_info[num], 1);
  269. num++;
  270. #endif
  271. #ifdef CONFIG_TSEC2
  272. SET_STD_TSEC_INFO(tsec_info[num], 2);
  273. num++;
  274. #endif
  275. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  276. mdio_info.name = DEFAULT_MII_NAME;
  277. fsl_pq_mdio_init(bis, &mdio_info);
  278. return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
  279. }
  280. #ifdef CONFIG_OF_BOARD_SETUP
  281. int ft_board_setup(void *blob, struct bd_info *bd)
  282. {
  283. phys_addr_t base;
  284. phys_size_t size;
  285. ft_cpu_setup(blob, bd);
  286. base = env_get_bootm_low();
  287. size = env_get_bootm_size();
  288. fdt_fixup_memory(blob, (u64)base, (u64)size);
  289. #ifdef CONFIG_HAS_FSL_DR_USB
  290. fsl_fdt_fixup_dr_usb(blob, bd);
  291. #endif
  292. FT_FSL_PCI_SETUP;
  293. return 0;
  294. }
  295. #endif
  296. static void hydra_initialize(void)
  297. {
  298. unsigned int i;
  299. pci_dev_t devno;
  300. /* Find and probe all the matching PCI devices */
  301. for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
  302. u32 val;
  303. struct ihs_fpga *fpga;
  304. u32 versions;
  305. u32 fpga_version;
  306. u32 fpga_features;
  307. unsigned hardware_version;
  308. unsigned feature_uart_channels;
  309. unsigned feature_sb_channels;
  310. /* Try to enable I/O accesses and bus-mastering */
  311. val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  312. pci_write_config_dword(devno, PCI_COMMAND, val);
  313. /* Make sure it worked */
  314. pci_read_config_dword(devno, PCI_COMMAND, &val);
  315. if (!(val & PCI_COMMAND_MEMORY)) {
  316. puts("Can't enable I/O memory\n");
  317. continue;
  318. }
  319. if (!(val & PCI_COMMAND_MASTER)) {
  320. puts("Can't enable bus-mastering\n");
  321. continue;
  322. }
  323. /* read FPGA details */
  324. fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
  325. PCI_REGION_MEM);
  326. /* disable sideband clocks */
  327. writel(1, &fpga->control);
  328. versions = readl(&fpga->versions);
  329. fpga_version = readl(&fpga->fpga_version);
  330. fpga_features = readl(&fpga->fpga_features);
  331. hardware_version = versions & 0xf;
  332. feature_uart_channels = (fpga_features >> 6) & 0x1f;
  333. feature_sb_channels = fpga_features & 0x1f;
  334. printf("FPGA%d: ", i);
  335. switch (hardware_version) {
  336. case HWVER_100:
  337. printf("HW-Ver 1.00\n");
  338. break;
  339. case HWVER_110:
  340. printf("HW-Ver 1.10\n");
  341. break;
  342. case HWVER_120:
  343. printf("HW-Ver 1.20\n");
  344. break;
  345. default:
  346. printf("HW-Ver %d(not supported)\n",
  347. hardware_version);
  348. break;
  349. }
  350. printf(" FPGA V %d.%02d, features:",
  351. fpga_version / 100, fpga_version % 100);
  352. printf(" %d uart channel(s)", feature_uart_channels);
  353. printf(" %d sideband channel(s)\n", feature_sb_channels);
  354. }
  355. }
  356. #endif