lpddr2.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015, Freescale Semiconductor, Inc.
  4. */
  5. #include <asm/io.h>
  6. #include <asm/arch/imx-regs.h>
  7. #include <asm/arch/siul.h>
  8. #include <asm/arch/lpddr2.h>
  9. #include <asm/arch/mmdc.h>
  10. volatile int mscr_offset_ck0;
  11. void lpddr2_config_iomux(uint8_t module)
  12. {
  13. int i;
  14. switch (module) {
  15. case DDR0:
  16. mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0);
  17. writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0));
  18. writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0));
  19. writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1));
  20. writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0));
  21. writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1));
  22. for (i = _DDR0_DM0; i <= _DDR0_DM3; i++)
  23. writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
  24. for (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++)
  25. writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
  26. for (i = _DDR0_A0; i <= _DDR0_A9; i++)
  27. writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
  28. for (i = _DDR0_D0; i <= _DDR0_D31; i++)
  29. writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
  30. break;
  31. case DDR1:
  32. writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0));
  33. writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0));
  34. writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1));
  35. writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0));
  36. writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1));
  37. for (i = _DDR1_DM0; i <= _DDR1_DM3; i++)
  38. writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
  39. for (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++)
  40. writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
  41. for (i = _DDR1_A0; i <= _DDR1_A9; i++)
  42. writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
  43. for (i = _DDR1_D0; i <= _DDR1_D31; i++)
  44. writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
  45. break;
  46. }
  47. }
  48. void config_mmdc(uint8_t module)
  49. {
  50. unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR;
  51. writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR);
  52. writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0);
  53. writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1);
  54. writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2);
  55. writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP);
  56. writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC);
  57. writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC);
  58. writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR);
  59. writel(_MDCTL, mmdc_addr + MMDC_MDCTL);
  60. writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0);
  61. while (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) {
  62. }
  63. writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR);
  64. /* Perform ZQ calibration */
  65. writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL);
  66. writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL);
  67. while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) {
  68. }
  69. /* Enable MMDC with CS0 */
  70. writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL);
  71. /* Complete the initialization sequence as defined by JEDEC */
  72. writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR);
  73. writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR);
  74. writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR);
  75. writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR);
  76. /* Set the amount of DRAM */
  77. /* Set DQS settings based on board type */
  78. switch (module) {
  79. case MMDC0:
  80. writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP);
  81. writel(MMDC_MPRDDLCTL_MODULE0_VALUE,
  82. mmdc_addr + MMDC_MPRDDLCTL);
  83. writel(MMDC_MPWRDLCTL_MODULE0_VALUE,
  84. mmdc_addr + MMDC_MPWRDLCTL);
  85. writel(MMDC_MPDGCTRL0_MODULE0_VALUE,
  86. mmdc_addr + MMDC_MPDGCTRL0);
  87. writel(MMDC_MPDGCTRL1_MODULE0_VALUE,
  88. mmdc_addr + MMDC_MPDGCTRL1);
  89. break;
  90. case MMDC1:
  91. writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP);
  92. writel(MMDC_MPRDDLCTL_MODULE1_VALUE,
  93. mmdc_addr + MMDC_MPRDDLCTL);
  94. writel(MMDC_MPWRDLCTL_MODULE1_VALUE,
  95. mmdc_addr + MMDC_MPWRDLCTL);
  96. writel(MMDC_MPDGCTRL0_MODULE1_VALUE,
  97. mmdc_addr + MMDC_MPDGCTRL0);
  98. writel(MMDC_MPDGCTRL1_MODULE1_VALUE,
  99. mmdc_addr + MMDC_MPDGCTRL1);
  100. break;
  101. }
  102. writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD);
  103. writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC);
  104. writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF);
  105. writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL);
  106. writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR);
  107. }