eth.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011 Freescale Semiconductor, Inc.
  4. * Author: Mingkai Hu <Mingkai.hu@freescale.com>
  5. */
  6. /*
  7. * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
  8. * are provided by the three on-board PHY or by the standard Freescale
  9. * four-port SGMII riser card. We need to change the phy-handle in the
  10. * kernel dts file to point to the correct PHY according to serdes mux
  11. * and serdes protocol selection.
  12. */
  13. #include <common.h>
  14. #include <net.h>
  15. #include <netdev.h>
  16. #include <asm/fsl_serdes.h>
  17. #include <fm_eth.h>
  18. #include <fsl_mdio.h>
  19. #include <malloc.h>
  20. #include <fsl_dtsec.h>
  21. #include "cpld.h"
  22. #include "../common/fman.h"
  23. #ifdef CONFIG_FMAN_ENET
  24. /*
  25. * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
  26. * that the mapping must be determined dynamically, or that the lane maps to
  27. * something other than a board slot
  28. */
  29. static u8 lane_to_slot[] = {
  30. 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
  31. };
  32. static int riser_phy_addr[] = {
  33. CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
  34. CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
  35. CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
  36. CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
  37. };
  38. /*
  39. * Initialize the lane_to_slot[] array.
  40. *
  41. * On the P2040RDB board the mapping is controlled by CPLD register.
  42. */
  43. static void initialize_lane_to_slot(void)
  44. {
  45. u8 mux = CPLD_READ(serdes_mux);
  46. lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1;
  47. lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2;
  48. lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2;
  49. lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2;
  50. }
  51. /*
  52. * Given the following ...
  53. *
  54. * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
  55. * compatible string and 'addr' physical address)
  56. *
  57. * 2) An Fman port
  58. *
  59. * ... update the phy-handle property of the Ethernet node to point to the
  60. * right PHY. This assumes that we already know the PHY for each port.
  61. *
  62. * The offset of the Fman Ethernet node is also passed in for convenience, but
  63. * it is not used, and we recalculate the offset anyway.
  64. *
  65. * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
  66. * Inside the Fman, "ports" are things that connect to MACs. We only call them
  67. * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
  68. * and ports are the same thing.
  69. *
  70. */
  71. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  72. enum fm_port port, int offset)
  73. {
  74. phy_interface_t intf = fm_info_get_enet_if(port);
  75. char phy[16];
  76. int lane;
  77. u8 slot;
  78. switch (intf) {
  79. /* The RGMII PHY is identified by the MAC connected to it */
  80. case PHY_INTERFACE_MODE_RGMII:
  81. case PHY_INTERFACE_MODE_RGMII_TXID:
  82. case PHY_INTERFACE_MODE_RGMII_RXID:
  83. case PHY_INTERFACE_MODE_RGMII_ID:
  84. sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
  85. fdt_set_phy_handle(fdt, compat, addr, phy);
  86. break;
  87. /* The SGMII PHY is identified by the MAC connected to it */
  88. case PHY_INTERFACE_MODE_SGMII:
  89. lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
  90. if (lane < 0)
  91. return;
  92. slot = lane_to_slot[lane];
  93. if (slot) {
  94. sprintf(phy, "phy_sgmii_%x",
  95. CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
  96. + (port - FM1_DTSEC1));
  97. fdt_set_phy_handle(fdt, compat, addr, phy);
  98. } else {
  99. sprintf(phy, "phy_sgmii_%x",
  100. CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
  101. + (port - FM1_DTSEC1));
  102. fdt_set_phy_handle(fdt, compat, addr, phy);
  103. }
  104. break;
  105. case PHY_INTERFACE_MODE_XGMII:
  106. /* XAUI */
  107. lane = serdes_get_first_lane(XAUI_FM1);
  108. if (lane >= 0) {
  109. /* The XAUI PHY is identified by the slot */
  110. sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
  111. fdt_set_phy_handle(fdt, compat, addr, phy);
  112. }
  113. break;
  114. default:
  115. break;
  116. }
  117. }
  118. #endif /* #ifdef CONFIG_FMAN_ENET */
  119. int board_eth_init(struct bd_info *bis)
  120. {
  121. #ifdef CONFIG_FMAN_ENET
  122. struct fsl_pq_mdio_info dtsec_mdio_info;
  123. struct tgec_mdio_info tgec_mdio_info;
  124. unsigned int i, slot;
  125. int lane;
  126. printf("Initializing Fman\n");
  127. initialize_lane_to_slot();
  128. dtsec_mdio_info.regs =
  129. (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
  130. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  131. /* Register the real 1G MDIO bus */
  132. fsl_pq_mdio_init(bis, &dtsec_mdio_info);
  133. tgec_mdio_info.regs =
  134. (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  135. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  136. /* Register the real 10G MDIO bus */
  137. fm_tgec_mdio_init(bis, &tgec_mdio_info);
  138. /*
  139. * Program the three on-board SGMII PHY addresses. If the SGMII Riser
  140. * card used, we'll override the PHY address later. For any DTSEC that
  141. * is RGMII, we'll also override its PHY address later. We assume that
  142. * DTSEC4 and DTSEC5 are used for RGMII.
  143. */
  144. fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
  145. fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
  146. fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
  147. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  148. int idx = i - FM1_DTSEC1;
  149. switch (fm_info_get_enet_if(i)) {
  150. case PHY_INTERFACE_MODE_SGMII:
  151. lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
  152. if (lane < 0)
  153. break;
  154. slot = lane_to_slot[lane];
  155. if (slot)
  156. fm_info_set_phy_address(i, riser_phy_addr[i]);
  157. break;
  158. case PHY_INTERFACE_MODE_RGMII:
  159. case PHY_INTERFACE_MODE_RGMII_TXID:
  160. case PHY_INTERFACE_MODE_RGMII_RXID:
  161. case PHY_INTERFACE_MODE_RGMII_ID:
  162. /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
  163. fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
  164. CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
  165. CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
  166. break;
  167. default:
  168. printf("Fman1: DTSEC%u set to unknown interface %i\n",
  169. idx + 1, fm_info_get_enet_if(i));
  170. break;
  171. }
  172. fm_info_set_mdio(i,
  173. miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
  174. }
  175. lane = serdes_get_first_lane(XAUI_FM1);
  176. if (lane >= 0) {
  177. slot = lane_to_slot[lane];
  178. if (slot)
  179. fm_info_set_phy_address(FM1_10GEC1,
  180. CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
  181. }
  182. fm_info_set_mdio(FM1_10GEC1,
  183. miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
  184. cpu_eth_init(bis);
  185. #endif
  186. return pci_eth_init(bis);
  187. }