tlb.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/mmu.h>
  7. struct fsl_e_tlb_entry tlb_table[] = {
  8. /* TLB 0 - for temp stack in cache */
  9. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  10. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  11. 0, 0, BOOKE_PAGESZ_4K, 0),
  12. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
  13. CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  14. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  15. 0, 0, BOOKE_PAGESZ_4K, 0),
  16. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
  17. CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  18. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  19. 0, 0, BOOKE_PAGESZ_4K, 0),
  20. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
  21. CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  22. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  23. 0, 0, BOOKE_PAGESZ_4K, 0),
  24. /* TLB 1 */
  25. /* *I*** - Covers boot page */
  26. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  27. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  28. 0, 0, BOOKE_PAGESZ_4K, 1),
  29. #ifdef CONFIG_SPL_NAND_BOOT
  30. SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
  31. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  32. 0, 10, BOOKE_PAGESZ_4K, 1),
  33. #endif
  34. /* *I*G* - CCSRBAR */
  35. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  36. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  37. 0, 1, BOOKE_PAGESZ_1M, 1),
  38. #ifndef CONFIG_SPL_BUILD
  39. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  40. MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  41. 0, 2, BOOKE_PAGESZ_16M, 1),
  42. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
  43. CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
  44. MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  45. 0, 3, BOOKE_PAGESZ_16M, 1),
  46. #ifdef CONFIG_PCI
  47. /* *I*G* - PCI */
  48. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  49. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  50. 0, 4, BOOKE_PAGESZ_1G, 1),
  51. /* *I*G* - PCI I/O */
  52. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  53. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54. 0, 5, BOOKE_PAGESZ_256K, 1),
  55. #endif
  56. #endif
  57. /* *I*G - Board CPLD */
  58. SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
  59. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  60. 0, 6, BOOKE_PAGESZ_256K, 1),
  61. SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  62. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  63. 0, 7, BOOKE_PAGESZ_1M, 1),
  64. #if defined(CONFIG_SYS_RAMBOOT) || \
  65. (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
  66. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  67. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  68. 0, 8, BOOKE_PAGESZ_1G, 1),
  69. #endif
  70. #ifdef CONFIG_SYS_INIT_L2_ADDR
  71. /* *I*G - L2SRAM */
  72. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
  73. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
  74. 0, 11, BOOKE_PAGESZ_256K, 1)
  75. #endif
  76. };
  77. int num_tlb_entries = ARRAY_SIZE(tlb_table);