p1010rdb.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <image.h>
  9. #include <init.h>
  10. #include <net.h>
  11. #include <asm/processor.h>
  12. #include <asm/mmu.h>
  13. #include <asm/cache.h>
  14. #include <asm/immap_85xx.h>
  15. #include <asm/io.h>
  16. #include <env.h>
  17. #include <miiphy.h>
  18. #include <linux/libfdt.h>
  19. #include <fdt_support.h>
  20. #include <fsl_mdio.h>
  21. #include <tsec.h>
  22. #include <mmc.h>
  23. #include <netdev.h>
  24. #include <pci.h>
  25. #include <asm/fsl_serdes.h>
  26. #include <fsl_ifc.h>
  27. #include <asm/fsl_pci.h>
  28. #include <hwconfig.h>
  29. #include <i2c.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #define GPIO4_PCIE_RESET_SET 0x08000000
  32. #define MUX_CPLD_CAN_UART 0x00
  33. #define MUX_CPLD_TDM 0x01
  34. #define MUX_CPLD_SPICS0_FLASH 0x00
  35. #define MUX_CPLD_SPICS0_SLIC 0x02
  36. #define PMUXCR1_IFC_MASK 0x00ffff00
  37. #define PMUXCR1_SDHC_MASK 0x00fff000
  38. #define PMUXCR1_SDHC_ENABLE 0x00555000
  39. enum {
  40. MUX_TYPE_IFC,
  41. MUX_TYPE_SDHC,
  42. MUX_TYPE_SPIFLASH,
  43. MUX_TYPE_TDM,
  44. MUX_TYPE_CAN,
  45. MUX_TYPE_CS0_NOR,
  46. MUX_TYPE_CS0_NAND,
  47. };
  48. enum {
  49. I2C_READ_BANK,
  50. I2C_READ_PCB_VER,
  51. };
  52. static uint sd_ifc_mux;
  53. struct cpld_data {
  54. u8 cpld_ver; /* cpld revision */
  55. #if defined(CONFIG_TARGET_P1010RDB_PA)
  56. u8 pcba_ver; /* pcb revision number */
  57. u8 twindie_ddr3;
  58. u8 res1[6];
  59. u8 bank_sel; /* NOR Flash bank */
  60. u8 res2[5];
  61. u8 usb2_sel;
  62. u8 res3[1];
  63. u8 porsw_sel;
  64. u8 tdm_can_sel;
  65. u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
  66. u8 por0; /* POR Options */
  67. u8 por1; /* POR Options */
  68. u8 por2; /* POR Options */
  69. u8 por3; /* POR Options */
  70. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  71. u8 rom_loc;
  72. #endif
  73. };
  74. int board_early_init_f(void)
  75. {
  76. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  77. struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  78. /* Clock configuration to access CPLD using IFC(GPCM) */
  79. setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
  80. /*
  81. * Reset PCIe slots via GPIO4
  82. */
  83. setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
  84. setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
  85. return 0;
  86. }
  87. int board_early_init_r(void)
  88. {
  89. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  90. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  91. /*
  92. * Remap Boot flash region to caching-inhibited
  93. * so that flash can be erased properly.
  94. */
  95. /* Flush d-cache and invalidate i-cache of any FLASH data */
  96. flush_dcache();
  97. invalidate_icache();
  98. if (flash_esel == -1) {
  99. /* very unlikely unless something is messed up */
  100. puts("Error: Could not find TLB for FLASH BASE\n");
  101. flash_esel = 2; /* give our best effort to continue */
  102. } else {
  103. /* invalidate existing TLB entry for flash */
  104. disable_tlb(flash_esel);
  105. }
  106. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  107. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  108. 0, flash_esel, BOOKE_PAGESZ_16M, 1);
  109. set_tlb(1, flashbase + 0x1000000,
  110. CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
  111. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  112. 0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
  113. return 0;
  114. }
  115. #if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
  116. void pci_init_board(void)
  117. {
  118. fsl_pcie_init_board(0);
  119. }
  120. #endif /* ifdef CONFIG_PCI */
  121. int config_board_mux(int ctrl_type)
  122. {
  123. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  124. u8 tmp;
  125. #ifdef CONFIG_DM_I2C
  126. struct udevice *dev;
  127. int ret;
  128. #if defined(CONFIG_TARGET_P1010RDB_PA)
  129. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  130. ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
  131. I2C_PCA9557_ADDR1, 1, &dev);
  132. if (ret) {
  133. printf("%s: Cannot find udev for a bus %d\n",
  134. __func__, I2C_PCA9557_BUS_NUM);
  135. return ret;
  136. }
  137. switch (ctrl_type) {
  138. case MUX_TYPE_IFC:
  139. tmp = 0xf0;
  140. dm_i2c_write(dev, 3, &tmp, 1);
  141. tmp = 0x01;
  142. dm_i2c_write(dev, 1, &tmp, 1);
  143. sd_ifc_mux = MUX_TYPE_IFC;
  144. clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
  145. break;
  146. case MUX_TYPE_SDHC:
  147. tmp = 0xf0;
  148. dm_i2c_write(dev, 3, &tmp, 1);
  149. tmp = 0x05;
  150. dm_i2c_write(dev, 1, &tmp, 1);
  151. sd_ifc_mux = MUX_TYPE_SDHC;
  152. clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
  153. PMUXCR1_SDHC_ENABLE);
  154. break;
  155. case MUX_TYPE_SPIFLASH:
  156. out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
  157. break;
  158. case MUX_TYPE_TDM:
  159. out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
  160. out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
  161. break;
  162. case MUX_TYPE_CAN:
  163. out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
  164. break;
  165. default:
  166. break;
  167. }
  168. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  169. ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
  170. I2C_PCA9557_ADDR2, 1, &dev);
  171. if (ret) {
  172. printf("%s: Cannot find udev for a bus %d\n",
  173. __func__, I2C_PCA9557_BUS_NUM);
  174. return ret;
  175. }
  176. switch (ctrl_type) {
  177. case MUX_TYPE_IFC:
  178. dm_i2c_read(dev, 0, &tmp, 1);
  179. clrbits_8(&tmp, 0x04);
  180. dm_i2c_write(dev, 1, &tmp, 1);
  181. dm_i2c_read(dev, 3, &tmp, 1);
  182. clrbits_8(&tmp, 0x04);
  183. dm_i2c_write(dev, 3, &tmp, 1);
  184. sd_ifc_mux = MUX_TYPE_IFC;
  185. clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
  186. break;
  187. case MUX_TYPE_SDHC:
  188. dm_i2c_read(dev, 0, &tmp, 1);
  189. setbits_8(&tmp, 0x04);
  190. dm_i2c_write(dev, 1, &tmp, 1);
  191. dm_i2c_read(dev, 3, &tmp, 1);
  192. clrbits_8(&tmp, 0x04);
  193. dm_i2c_write(dev, 3, &tmp, 1);
  194. sd_ifc_mux = MUX_TYPE_SDHC;
  195. clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
  196. PMUXCR1_SDHC_ENABLE);
  197. break;
  198. case MUX_TYPE_SPIFLASH:
  199. dm_i2c_read(dev, 0, &tmp, 1);
  200. clrbits_8(&tmp, 0x80);
  201. dm_i2c_write(dev, 1, &tmp, 1);
  202. dm_i2c_read(dev, 3, &tmp, 1);
  203. clrbits_8(&tmp, 0x80);
  204. dm_i2c_write(dev, 3, &tmp, 1);
  205. break;
  206. case MUX_TYPE_TDM:
  207. dm_i2c_read(dev, 0, &tmp, 1);
  208. setbits_8(&tmp, 0x82);
  209. dm_i2c_write(dev, 1, &tmp, 1);
  210. dm_i2c_read(dev, 3, &tmp, 1);
  211. clrbits_8(&tmp, 0x82);
  212. dm_i2c_write(dev, 3, &tmp, 1);
  213. break;
  214. case MUX_TYPE_CAN:
  215. dm_i2c_read(dev, 0, &tmp, 1);
  216. clrbits_8(&tmp, 0x02);
  217. dm_i2c_write(dev, 1, &tmp, 1);
  218. dm_i2c_read(dev, 3, &tmp, 1);
  219. clrbits_8(&tmp, 0x02);
  220. dm_i2c_write(dev, 3, &tmp, 1);
  221. break;
  222. case MUX_TYPE_CS0_NOR:
  223. dm_i2c_read(dev, 0, &tmp, 1);
  224. clrbits_8(&tmp, 0x08);
  225. dm_i2c_write(dev, 1, &tmp, 1);
  226. dm_i2c_read(dev, 3, &tmp, 1);
  227. clrbits_8(&tmp, 0x08);
  228. dm_i2c_write(dev, 3, &tmp, 1);
  229. break;
  230. case MUX_TYPE_CS0_NAND:
  231. dm_i2c_read(dev, 0, &tmp, 1);
  232. setbits_8(&tmp, 0x08);
  233. dm_i2c_write(dev, 1, &tmp, 1);
  234. dm_i2c_read(dev, 3, &tmp, 1);
  235. clrbits_8(&tmp, 0x08);
  236. dm_i2c_write(dev, 3, &tmp, 1);
  237. break;
  238. default:
  239. break;
  240. }
  241. #endif
  242. #else
  243. #if defined(CONFIG_TARGET_P1010RDB_PA)
  244. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  245. switch (ctrl_type) {
  246. case MUX_TYPE_IFC:
  247. i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
  248. tmp = 0xf0;
  249. i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
  250. tmp = 0x01;
  251. i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
  252. sd_ifc_mux = MUX_TYPE_IFC;
  253. clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
  254. break;
  255. case MUX_TYPE_SDHC:
  256. i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
  257. tmp = 0xf0;
  258. i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
  259. tmp = 0x05;
  260. i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
  261. sd_ifc_mux = MUX_TYPE_SDHC;
  262. clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
  263. PMUXCR1_SDHC_ENABLE);
  264. break;
  265. case MUX_TYPE_SPIFLASH:
  266. out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
  267. break;
  268. case MUX_TYPE_TDM:
  269. out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
  270. out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
  271. break;
  272. case MUX_TYPE_CAN:
  273. out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
  274. break;
  275. default:
  276. break;
  277. }
  278. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  279. uint orig_bus = i2c_get_bus_num();
  280. i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
  281. switch (ctrl_type) {
  282. case MUX_TYPE_IFC:
  283. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  284. clrbits_8(&tmp, 0x04);
  285. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  286. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  287. clrbits_8(&tmp, 0x04);
  288. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  289. sd_ifc_mux = MUX_TYPE_IFC;
  290. clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
  291. break;
  292. case MUX_TYPE_SDHC:
  293. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  294. setbits_8(&tmp, 0x04);
  295. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  296. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  297. clrbits_8(&tmp, 0x04);
  298. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  299. sd_ifc_mux = MUX_TYPE_SDHC;
  300. clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
  301. PMUXCR1_SDHC_ENABLE);
  302. break;
  303. case MUX_TYPE_SPIFLASH:
  304. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  305. clrbits_8(&tmp, 0x80);
  306. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  307. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  308. clrbits_8(&tmp, 0x80);
  309. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  310. break;
  311. case MUX_TYPE_TDM:
  312. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  313. setbits_8(&tmp, 0x82);
  314. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  315. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  316. clrbits_8(&tmp, 0x82);
  317. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  318. break;
  319. case MUX_TYPE_CAN:
  320. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  321. clrbits_8(&tmp, 0x02);
  322. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  323. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  324. clrbits_8(&tmp, 0x02);
  325. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  326. break;
  327. case MUX_TYPE_CS0_NOR:
  328. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  329. clrbits_8(&tmp, 0x08);
  330. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  331. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  332. clrbits_8(&tmp, 0x08);
  333. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  334. break;
  335. case MUX_TYPE_CS0_NAND:
  336. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  337. setbits_8(&tmp, 0x08);
  338. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  339. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  340. clrbits_8(&tmp, 0x08);
  341. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  342. break;
  343. default:
  344. break;
  345. }
  346. i2c_set_bus_num(orig_bus);
  347. #endif
  348. #endif
  349. return 0;
  350. }
  351. #ifdef CONFIG_TARGET_P1010RDB_PB
  352. int i2c_pca9557_read(int type)
  353. {
  354. u8 val;
  355. int bus_num = I2C_PCA9557_BUS_NUM;
  356. #ifdef CONFIG_DM_I2C
  357. struct udevice *dev;
  358. int ret;
  359. ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev);
  360. if (ret) {
  361. printf("%s: Cannot find udev for a bus %d\n",
  362. __func__, bus_num);
  363. return ret;
  364. }
  365. dm_i2c_read(dev, 0, &val, 1);
  366. #else
  367. i2c_set_bus_num(bus_num);
  368. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
  369. #endif
  370. switch (type) {
  371. case I2C_READ_BANK:
  372. val = (val & 0x10) >> 4;
  373. break;
  374. case I2C_READ_PCB_VER:
  375. val = ((val & 0x60) >> 5) + 1;
  376. break;
  377. default:
  378. break;
  379. }
  380. return val;
  381. }
  382. #endif
  383. int checkboard(void)
  384. {
  385. struct cpu_type *cpu;
  386. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  387. u8 val;
  388. cpu = gd->arch.cpu;
  389. #if defined(CONFIG_TARGET_P1010RDB_PA)
  390. printf("Board: %sRDB-PA, ", cpu->name);
  391. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  392. printf("Board: %sRDB-PB, ", cpu->name);
  393. #ifdef CONFIG_DM_I2C
  394. struct udevice *dev;
  395. int ret;
  396. ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2,
  397. 1, &dev);
  398. if (ret) {
  399. printf("%s: Cannot find udev for a bus %d\n", __func__,
  400. I2C_PCA9557_BUS_NUM);
  401. return ret;
  402. }
  403. val = 0x0; /* no polarity inversion */
  404. dm_i2c_write(dev, 2, &val, 1);
  405. #else
  406. i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
  407. i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
  408. val = 0x0; /* no polarity inversion */
  409. i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
  410. #endif
  411. #endif
  412. #ifdef CONFIG_SDCARD
  413. /* switch to IFC to read info from CPLD */
  414. config_board_mux(MUX_TYPE_IFC);
  415. #endif
  416. #if defined(CONFIG_TARGET_P1010RDB_PA)
  417. val = (in_8(&cpld_data->pcba_ver) & 0xf);
  418. printf("PCB: v%x.0\n", val);
  419. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  420. val = in_8(&cpld_data->cpld_ver);
  421. printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
  422. printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
  423. val = in_8(&cpld_data->rom_loc) & 0xf;
  424. puts("Boot from: ");
  425. switch (val) {
  426. case 0xf:
  427. config_board_mux(MUX_TYPE_CS0_NOR);
  428. printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
  429. break;
  430. case 0xe:
  431. puts("SDHC\n");
  432. val = 0x60; /* set pca9557 pin input/output */
  433. #ifdef CONFIG_DM_I2C
  434. dm_i2c_write(dev, 3, &val, 1);
  435. #else
  436. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
  437. #endif
  438. break;
  439. case 0x5:
  440. config_board_mux(MUX_TYPE_IFC);
  441. config_board_mux(MUX_TYPE_CS0_NAND);
  442. puts("NAND\n");
  443. break;
  444. case 0x6:
  445. config_board_mux(MUX_TYPE_IFC);
  446. puts("SPI\n");
  447. break;
  448. default:
  449. puts("unknown\n");
  450. break;
  451. }
  452. #endif
  453. return 0;
  454. }
  455. #ifndef CONFIG_DM_ETH
  456. int board_eth_init(struct bd_info *bis)
  457. {
  458. #ifdef CONFIG_TSEC_ENET
  459. struct fsl_pq_mdio_info mdio_info;
  460. struct tsec_info_struct tsec_info[4];
  461. struct cpu_type *cpu;
  462. int num = 0;
  463. cpu = gd->arch.cpu;
  464. #ifdef CONFIG_TSEC1
  465. SET_STD_TSEC_INFO(tsec_info[num], 1);
  466. num++;
  467. #endif
  468. #ifdef CONFIG_TSEC2
  469. SET_STD_TSEC_INFO(tsec_info[num], 2);
  470. num++;
  471. #endif
  472. #ifdef CONFIG_TSEC3
  473. /* P1014 and it's derivatives do not support eTSEC3 */
  474. if (cpu->soc_ver != SVR_P1014) {
  475. SET_STD_TSEC_INFO(tsec_info[num], 3);
  476. num++;
  477. }
  478. #endif
  479. if (!num) {
  480. printf("No TSECs initialized\n");
  481. return 0;
  482. }
  483. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  484. mdio_info.name = DEFAULT_MII_NAME;
  485. fsl_pq_mdio_init(bis, &mdio_info);
  486. tsec_eth_init(bis, tsec_info, num);
  487. #endif
  488. return pci_eth_init(bis);
  489. }
  490. #endif
  491. #if defined(CONFIG_OF_BOARD_SETUP)
  492. void fdt_del_flexcan(void *blob)
  493. {
  494. int nodeoff = 0;
  495. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  496. "fsl,p1010-flexcan")) >= 0) {
  497. fdt_del_node(blob, nodeoff);
  498. }
  499. }
  500. void fdt_del_spi_flash(void *blob)
  501. {
  502. int nodeoff = 0;
  503. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  504. "spansion,s25sl12801")) >= 0) {
  505. fdt_del_node(blob, nodeoff);
  506. }
  507. }
  508. void fdt_del_spi_slic(void *blob)
  509. {
  510. int nodeoff = 0;
  511. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  512. "zarlink,le88266")) >= 0) {
  513. fdt_del_node(blob, nodeoff);
  514. }
  515. }
  516. void fdt_del_tdm(void *blob)
  517. {
  518. int nodeoff = 0;
  519. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  520. "fsl,starlite-tdm")) >= 0) {
  521. fdt_del_node(blob, nodeoff);
  522. }
  523. }
  524. void fdt_del_sdhc(void *blob)
  525. {
  526. int nodeoff = 0;
  527. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  528. "fsl,esdhc")) >= 0) {
  529. fdt_del_node(blob, nodeoff);
  530. }
  531. }
  532. void fdt_del_ifc(void *blob)
  533. {
  534. int nodeoff = 0;
  535. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  536. "fsl,ifc")) >= 0) {
  537. fdt_del_node(blob, nodeoff);
  538. }
  539. }
  540. void fdt_disable_uart1(void *blob)
  541. {
  542. int nodeoff;
  543. nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
  544. CONFIG_SYS_NS16550_COM2);
  545. if (nodeoff > 0) {
  546. fdt_status_disabled(blob, nodeoff);
  547. } else {
  548. printf("WARNING unable to set status for fsl,ns16550 "
  549. "uart1: %s\n", fdt_strerror(nodeoff));
  550. }
  551. }
  552. int ft_board_setup(void *blob, struct bd_info *bd)
  553. {
  554. phys_addr_t base;
  555. phys_size_t size;
  556. struct cpu_type *cpu;
  557. cpu = gd->arch.cpu;
  558. ft_cpu_setup(blob, bd);
  559. base = env_get_bootm_low();
  560. size = env_get_bootm_size();
  561. #if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
  562. FT_FSL_PCI_SETUP;
  563. #endif
  564. fdt_fixup_memory(blob, (u64)base, (u64)size);
  565. #if defined(CONFIG_HAS_FSL_DR_USB)
  566. fsl_fdt_fixup_dr_usb(blob, bd);
  567. #endif
  568. /* P1014 and it's derivatives don't support CAN and eTSEC3 */
  569. if (cpu->soc_ver == SVR_P1014) {
  570. fdt_del_flexcan(blob);
  571. fdt_del_node_and_alias(blob, "ethernet2");
  572. }
  573. /* Delete IFC node as IFC pins are multiplexing with SDHC */
  574. if (sd_ifc_mux != MUX_TYPE_IFC)
  575. fdt_del_ifc(blob);
  576. else
  577. fdt_del_sdhc(blob);
  578. if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
  579. fdt_del_tdm(blob);
  580. fdt_del_spi_slic(blob);
  581. } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
  582. fdt_del_flexcan(blob);
  583. fdt_del_spi_flash(blob);
  584. fdt_disable_uart1(blob);
  585. } else {
  586. /*
  587. * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
  588. * explicitly, defaultly spi_cs_sel to spi-flash instead of
  589. * to tdm/slic.
  590. */
  591. fdt_del_tdm(blob);
  592. fdt_del_flexcan(blob);
  593. fdt_disable_uart1(blob);
  594. }
  595. return 0;
  596. }
  597. #endif
  598. #ifdef CONFIG_SDCARD
  599. int board_mmc_init(struct bd_info *bis)
  600. {
  601. config_board_mux(MUX_TYPE_SDHC);
  602. return -1;
  603. }
  604. #else
  605. void board_reset(void)
  606. {
  607. /* mux to IFC to enable CPLD for reset */
  608. if (sd_ifc_mux != MUX_TYPE_IFC)
  609. config_board_mux(MUX_TYPE_IFC);
  610. }
  611. #endif
  612. int misc_init_r(void)
  613. {
  614. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  615. if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
  616. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
  617. MPC85xx_PMUXCR_CAN1_UART |
  618. MPC85xx_PMUXCR_CAN2_TDM |
  619. MPC85xx_PMUXCR_CAN2_UART);
  620. config_board_mux(MUX_TYPE_CAN);
  621. } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
  622. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
  623. MPC85xx_PMUXCR_CAN1_UART);
  624. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
  625. MPC85xx_PMUXCR_CAN1_TDM);
  626. clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
  627. setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
  628. config_board_mux(MUX_TYPE_TDM);
  629. } else {
  630. /* defaultly spi_cs_sel to flash */
  631. config_board_mux(MUX_TYPE_SPIFLASH);
  632. }
  633. if (hwconfig("esdhc"))
  634. config_board_mux(MUX_TYPE_SDHC);
  635. else if (hwconfig("ifc"))
  636. config_board_mux(MUX_TYPE_IFC);
  637. #ifdef CONFIG_TARGET_P1010RDB_PB
  638. setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
  639. #endif
  640. return 0;
  641. }
  642. #ifndef CONFIG_SPL_BUILD
  643. static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
  644. char *const argv[])
  645. {
  646. if (argc < 2)
  647. return CMD_RET_USAGE;
  648. if (strcmp(argv[1], "ifc") == 0)
  649. config_board_mux(MUX_TYPE_IFC);
  650. else if (strcmp(argv[1], "sdhc") == 0)
  651. config_board_mux(MUX_TYPE_SDHC);
  652. else
  653. return CMD_RET_USAGE;
  654. return 0;
  655. }
  656. U_BOOT_CMD(
  657. mux, 2, 0, pin_mux_cmd,
  658. "configure multiplexing pin for IFC/SDHC bus in runtime",
  659. "bus_type (e.g. mux sdhc)"
  660. );
  661. #endif