README.P1010RDB-PB 6.4 KB

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  1. Overview
  2. =========
  3. The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
  4. P1010RDB-PB is a variation of previous P1010RDB-PA board.
  5. The P1010 is a cost-effective, low-power, highly integrated host processor
  6. based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that
  7. addresses the requirements of several routing, gateways, storage, consumer,
  8. and industrial applications. Applications of interest include the main CPUs and
  9. I/O processors in network attached storage (NAS), the voice over IP (VoIP)
  10. router/gateway, and wireless LAN (WLAN) and industrial controllers.
  11. The P1010RDB-PB board features are as following:
  12. Memory subsystem:
  13. - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
  14. - 32M bytes NOR flash single-chip memory
  15. - 2G bytes NAND flash memory
  16. - 16M bytes SPI memory
  17. - 256K bit M24256 I2C EEPROM
  18. - I2C Board EEPROM 128x8 bit memory
  19. - SD/MMC connector to interface with the SD memory card
  20. Interfaces:
  21. - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII)
  22. - PCIe 2.0: two x1 mini-PCIe slots
  23. - SATA 2.0: two SATA interfaces
  24. - USB 2.0: one USB interface
  25. - FlexCAN: two FlexCAN interfaces (revision 2.0B)
  26. - UART: one USB-to-Serial interface
  27. - TDM: 2 FXS ports connected via an external SLIC to the TDM interface.
  28. 1 FXO port connected via a relay to FXS for switchover to POTS
  29. Board connectors:
  30. - Mini-ITX power supply connector
  31. - JTAG/COP for debugging
  32. POR: support critical POR setting changed via switch on board
  33. PCB: 6-layer routing (4-layer signals, 2-layer power and ground)
  34. Physical Memory Map on P1010RDB
  35. ===============================
  36. Address Start Address End Memory type Attributes
  37. 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
  38. 0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
  39. 0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
  40. 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
  41. 0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
  42. 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
  43. 0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
  44. 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  45. Serial Port Configuration on P1010RDB
  46. =====================================
  47. Configure the serial port of the attached computer with the following values:
  48. -Data rate: 115200 bps
  49. -Number of data bits: 8
  50. -Parity: None
  51. -Number of Stop bits: 1
  52. -Flow Control: Hardware/None
  53. P1010RDB-PB default DIP-switch settings
  54. =======================================
  55. SW1[1:8]= 10101010
  56. SW2[1:8]= 11011000
  57. SW3[1:8]= 10010000
  58. SW4[1:4]= 1010
  59. SW5[1:8]= 11111010
  60. P1010RDB-PB boot mode settings via DIP-switch
  61. =============================================
  62. SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot
  63. SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
  64. SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
  65. SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot
  66. Note: 1 stands for 'on', 0 stands for 'off'
  67. Switch P1010RDB-PB boot mode via software without setting DIP-switch
  68. ====================================================================
  69. => run boot_bank0 (boot from NOR bank0)
  70. => run boot_bank1 (boot from NOR bank1)
  71. => run boot_nand (boot from NAND flash)
  72. => run boot_spi (boot from SPI flash)
  73. => run boot_sd (boot from SD card)
  74. Frequency combination support on P1010RDB-PB
  75. =============================================
  76. SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s)
  77. 0101 1 1010 0 800 400 800
  78. 1001 1 1010 0 800 400 667
  79. 1010 1 1100 0 667 333 667
  80. 1000 0 1010 0 533 266 667
  81. 0101 1 1010 1 1000 400 800
  82. 1001 1 1010 1 1000 400 667
  83. Setting of pin mux
  84. ==================
  85. Since pins multiplexing, TDM and CAN are muxed with SPI flash.
  86. SDHC is muxed with IFC. IFC and SPI flash are enabled by default.
  87. To enable TDM:
  88. => setenv hwconfig fsl_p1010mux:tdm_can=tdm
  89. => save;reset
  90. To enable FlexCAN:
  91. => setenv hwconfig fsl_p1010mux:tdm_can=can
  92. => save;reset
  93. To enable SDHC in case of NOR/NAND/SPI boot
  94. a) For temporary use case in runtime without reboot system
  95. run 'mux sdhc' in U-Boot to validate SDHC with invalidating IFC.
  96. b) For long-term use case
  97. set 'esdhc' in hwconfig and save it.
  98. To enable IFC in case of SD boot
  99. a) For temporary use case in runtime without reboot system
  100. run 'mux ifc' in U-Boot to validate IFC with invalidating SDHC.
  101. b) For long-term use case
  102. set 'ifc' in hwconfig and save it.
  103. Build images for different boot mode
  104. ====================================
  105. First setup cross compile environment on build host
  106. $ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu-
  107. 1. For NOR boot
  108. $ make P1010RDB-PB_NOR
  109. 2. For NAND boot
  110. $ make P1010RDB-PB_NAND
  111. 3. For SPI boot
  112. $ make P1010RDB-PB_SPIFLASH
  113. 4. For SD boot
  114. $ make P1010RDB-PB_SDCARD
  115. Steps to program images to flash for different boot mode
  116. ========================================================
  117. 1. NOR boot
  118. => tftp 1000000 u-boot.bin
  119. For bank0
  120. => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
  121. set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
  122. For bank1
  123. => pro off all;era eef40000 eeffffff;cp.b 1000000 eef40000 $filesize
  124. set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
  125. 2. NAND boot
  126. => tftp 1000000 u-boot-nand.bin
  127. => nand erase 0 $filesize; nand write $loadaddr 0 $filesize
  128. Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board
  129. 3. SPI boot
  130. 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin
  131. 2) => tftp 1000000 u-boot-spi-combined.bin
  132. 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000
  133. set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board
  134. 4. SD boot
  135. 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin
  136. 2) => tftp 1000000 u-boot-sd-combined.bin
  137. 3) => mux sdhc
  138. 4) => mmc write 1000000 0 1050
  139. set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board
  140. Boot Linux from network using TFTP on P1010RDB-PB
  141. =================================================
  142. Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path.
  143. => tftp 1000000 uImage
  144. => tftp 2000000 p1010rdb.dtb
  145. => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
  146. => bootm 1000000 3000000 2000000
  147. For more details, please refer to P1010RDB-PB User Guide and access website
  148. www.freescale.com and Freescale QorIQ SDK Infocenter document.