mx7dsabresd.c 8.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <init.h>
  6. #include <net.h>
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/mx7-pins.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/gpio.h>
  12. #include <asm/mach-imx/iomux-v3.h>
  13. #include <asm/io.h>
  14. #include <linux/delay.h>
  15. #include <linux/sizes.h>
  16. #include <common.h>
  17. #include <fsl_esdhc_imx.h>
  18. #include <mmc.h>
  19. #include <miiphy.h>
  20. #include <power/pmic.h>
  21. #include <power/pfuze3000_pmic.h>
  22. #include "../common/pfuze.h"
  23. #include <i2c.h>
  24. #include <asm/mach-imx/mxc_i2c.h>
  25. #include <asm/arch/crm_regs.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
  28. PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  29. #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  30. PAD_CTL_DSE_3P3V_49OHM)
  31. #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  32. #define SPI_PAD_CTRL \
  33. (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)
  34. #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
  35. #ifdef CONFIG_MXC_SPI
  36. static iomux_v3_cfg_t const ecspi3_pads[] = {
  37. MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  38. MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  39. MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  40. MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  41. };
  42. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  43. {
  44. return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1;
  45. }
  46. static void setup_spi(void)
  47. {
  48. imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
  49. }
  50. #endif
  51. int dram_init(void)
  52. {
  53. gd->ram_size = PHYS_SDRAM_SIZE;
  54. return 0;
  55. }
  56. static iomux_v3_cfg_t const wdog_pads[] = {
  57. MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  58. };
  59. static iomux_v3_cfg_t const uart1_pads[] = {
  60. MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  61. MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  62. };
  63. #ifdef CONFIG_NAND_MXS
  64. static iomux_v3_cfg_t const gpmi_pads[] = {
  65. MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  66. MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  67. MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  68. MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  69. MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  70. MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  71. MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  72. MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  73. MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  74. MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  75. MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  76. MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  77. MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  78. MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  79. MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  80. MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  81. MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  82. MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
  83. MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
  84. };
  85. static void setup_gpmi_nand(void)
  86. {
  87. imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
  88. /* NAND_USDHC_BUS_CLK is set in rom */
  89. set_clk_nand();
  90. }
  91. #endif
  92. #ifdef CONFIG_VIDEO_MXS
  93. static iomux_v3_cfg_t const lcd_pads[] = {
  94. MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
  95. MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
  96. MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  97. MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  98. MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  99. MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  100. MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  101. MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  102. MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  103. MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  104. MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  105. MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  106. MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  107. MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  108. MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  109. MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  110. MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  111. MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  112. MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  113. MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  114. MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  115. MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  116. MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  117. MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  118. MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  119. MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  120. MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  121. MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  122. MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  123. };
  124. static iomux_v3_cfg_t const pwm_pads[] = {
  125. /* Use GPIO for Brightness adjustment, duty cycle = period */
  126. MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
  127. };
  128. static int setup_lcd(void)
  129. {
  130. imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  131. imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
  132. /* Reset LCD */
  133. gpio_request(IMX_GPIO_NR(3, 4), "lcd reset");
  134. gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
  135. udelay(500);
  136. gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
  137. /* Set Brightness to high */
  138. gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight");
  139. gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
  140. return 0;
  141. }
  142. #endif
  143. static void setup_iomux_uart(void)
  144. {
  145. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  146. }
  147. int board_mmc_get_env_dev(int devno)
  148. {
  149. if (devno == 2)
  150. devno--;
  151. return devno;
  152. }
  153. int mmc_map_to_kernel_blk(int dev_no)
  154. {
  155. if (dev_no == 1)
  156. dev_no++;
  157. return dev_no;
  158. }
  159. #ifdef CONFIG_FEC_MXC
  160. static int setup_fec(void)
  161. {
  162. struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  163. = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
  164. /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
  165. clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  166. (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
  167. IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
  168. return set_clk_enet(ENET_125MHZ);
  169. }
  170. int board_phy_config(struct phy_device *phydev)
  171. {
  172. /* enable rgmii rxc skew and phy mode select to RGMII copper */
  173. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
  174. phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
  175. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
  176. phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
  177. if (phydev->drv->config)
  178. phydev->drv->config(phydev);
  179. return 0;
  180. }
  181. #endif
  182. #ifdef CONFIG_FSL_QSPI
  183. int board_qspi_init(void)
  184. {
  185. /* Set the clock */
  186. set_clk_qspi();
  187. return 0;
  188. }
  189. #endif
  190. int board_early_init_f(void)
  191. {
  192. setup_iomux_uart();
  193. return 0;
  194. }
  195. int board_init(void)
  196. {
  197. /* address of boot parameters */
  198. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  199. #ifdef CONFIG_FEC_MXC
  200. setup_fec();
  201. #endif
  202. #ifdef CONFIG_NAND_MXS
  203. setup_gpmi_nand();
  204. #endif
  205. #ifdef CONFIG_VIDEO_MXS
  206. setup_lcd();
  207. #endif
  208. #ifdef CONFIG_FSL_QSPI
  209. board_qspi_init();
  210. #endif
  211. #ifdef CONFIG_MXC_SPI
  212. setup_spi();
  213. #endif
  214. return 0;
  215. }
  216. #ifdef CONFIG_DM_PMIC
  217. int power_init_board(void)
  218. {
  219. struct udevice *dev;
  220. int ret, dev_id, rev_id;
  221. ret = pmic_get("pfuze3000@8", &dev);
  222. if (ret == -ENODEV)
  223. return 0;
  224. if (ret != 0)
  225. return ret;
  226. dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
  227. rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
  228. printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  229. pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
  230. /*
  231. * Set the voltage of VLDO4 output to 2.8V which feeds
  232. * the MIPI DSI and MIPI CSI inputs.
  233. */
  234. pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA);
  235. return 0;
  236. }
  237. #endif
  238. int board_late_init(void)
  239. {
  240. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  241. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  242. set_wdog_reset(wdog);
  243. /*
  244. * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
  245. * since we use PMIC_PWRON to reset the board.
  246. */
  247. clrsetbits_le16(&wdog->wcr, 0, 0x10);
  248. return 0;
  249. }
  250. int checkboard(void)
  251. {
  252. char *mode;
  253. if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
  254. mode = "secure";
  255. else
  256. mode = "non-secure";
  257. printf("Board: i.MX7D SABRESD in %s mode\n", mode);
  258. return 0;
  259. }