mx6sxsabresd.c 9.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  6. */
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/crm_regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/mx6-pins.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/gpio.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <asm/io.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <env.h>
  20. #include <linux/delay.h>
  21. #include <linux/sizes.h>
  22. #include <common.h>
  23. #include <fsl_esdhc_imx.h>
  24. #include <mmc.h>
  25. #include <i2c.h>
  26. #include <miiphy.h>
  27. #include <netdev.h>
  28. #include <power/pmic.h>
  29. #include <power/pfuze100_pmic.h>
  30. #include "../common/pfuze.h"
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  33. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  34. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  35. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  36. PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  37. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  38. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  39. PAD_CTL_SPEED_HIGH | \
  40. PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  41. #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  42. PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  43. #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  44. PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
  45. #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  46. PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  47. #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
  48. PAD_CTL_DSE_40ohm)
  49. int dram_init(void)
  50. {
  51. gd->ram_size = imx_ddr_size();
  52. return 0;
  53. }
  54. static iomux_v3_cfg_t const uart1_pads[] = {
  55. MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  56. MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  57. };
  58. static iomux_v3_cfg_t const wdog_b_pad = {
  59. MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  60. };
  61. static iomux_v3_cfg_t const fec1_pads[] = {
  62. MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  63. MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  64. MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  65. MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  66. MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  67. MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  68. MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  69. MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  70. MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71. MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72. MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73. MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74. MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  75. MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  76. };
  77. static iomux_v3_cfg_t const peri_3v3_pads[] = {
  78. MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
  79. };
  80. static iomux_v3_cfg_t const phy_control_pads[] = {
  81. /* 25MHz Ethernet PHY Clock */
  82. MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  83. /* ENET PHY Power */
  84. MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
  85. /* AR8031 PHY Reset */
  86. MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
  87. };
  88. static void setup_iomux_uart(void)
  89. {
  90. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  91. }
  92. static int setup_fec(void)
  93. {
  94. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  95. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  96. int reg, ret;
  97. /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
  98. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
  99. ret = enable_fec_anatop_clock(0, ENET_125MHZ);
  100. if (ret)
  101. return ret;
  102. imx_iomux_v3_setup_multiple_pads(phy_control_pads,
  103. ARRAY_SIZE(phy_control_pads));
  104. /* Enable the ENET power, active low */
  105. gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
  106. gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
  107. /* Reset AR8031 PHY */
  108. gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
  109. gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
  110. mdelay(10);
  111. gpio_set_value(IMX_GPIO_NR(2, 7), 1);
  112. reg = readl(&anatop->pll_enet);
  113. reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
  114. writel(reg, &anatop->pll_enet);
  115. return 0;
  116. }
  117. int board_eth_init(struct bd_info *bis)
  118. {
  119. imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
  120. setup_fec();
  121. return cpu_eth_init(bis);
  122. }
  123. int power_init_board(void)
  124. {
  125. struct udevice *dev;
  126. unsigned int reg;
  127. int ret;
  128. dev = pfuze_common_init();
  129. if (!dev)
  130. return -ENODEV;
  131. ret = pfuze_mode_init(dev, APS_PFM);
  132. if (ret < 0)
  133. return ret;
  134. /* Enable power of VGEN5 3V3, needed for SD3 */
  135. reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
  136. reg &= ~LDO_VOL_MASK;
  137. reg |= (LDOB_3_30V | (1 << LDO_EN));
  138. pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
  139. return 0;
  140. }
  141. int board_phy_config(struct phy_device *phydev)
  142. {
  143. /*
  144. * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
  145. * Phy control debug reg 0
  146. */
  147. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  148. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  149. /* rgmii tx clock delay enable */
  150. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  151. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  152. if (phydev->drv->config)
  153. phydev->drv->config(phydev);
  154. return 0;
  155. }
  156. int board_early_init_f(void)
  157. {
  158. setup_iomux_uart();
  159. /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
  160. imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
  161. ARRAY_SIZE(peri_3v3_pads));
  162. return 0;
  163. }
  164. int board_mmc_get_env_dev(int devno)
  165. {
  166. return devno;
  167. }
  168. #ifdef CONFIG_FSL_QSPI
  169. int board_qspi_init(void)
  170. {
  171. /* Set the clock */
  172. enable_qspi_clk(1);
  173. return 0;
  174. }
  175. #endif
  176. #ifdef CONFIG_VIDEO_MXS
  177. static iomux_v3_cfg_t const lcd_pads[] = {
  178. MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
  179. MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
  180. MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  181. MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  182. MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  183. MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  184. MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  185. MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  186. MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  187. MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  188. MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  189. MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  190. MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  191. MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  192. MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  193. MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  194. MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  195. MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  196. MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  197. MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  198. MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  199. MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  200. MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  201. MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  202. MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  203. MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  204. MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  205. MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  206. MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  207. /* Use GPIO for Brightness adjustment, duty cycle = period */
  208. MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
  209. };
  210. static int setup_lcd(void)
  211. {
  212. enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
  213. imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  214. /* Reset the LCD */
  215. gpio_request(IMX_GPIO_NR(3, 27), "lcd_rst");
  216. gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
  217. udelay(500);
  218. gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
  219. /* Set Brightness to high */
  220. gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
  221. gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
  222. return 0;
  223. }
  224. #endif
  225. int board_init(void)
  226. {
  227. /* Address of boot parameters */
  228. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  229. /*
  230. * Because kernel set WDOG_B mux before pad with the common pinctrl
  231. * framwork now and wdog reset will be triggered once set WDOG_B mux
  232. * with default pad setting, we set pad setting here to workaround this.
  233. * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
  234. * as GPIO mux firstly here to workaround it.
  235. */
  236. imx_iomux_v3_setup_pad(wdog_b_pad);
  237. /* Active high for ncp692 */
  238. gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
  239. gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
  240. #ifdef CONFIG_FSL_QSPI
  241. board_qspi_init();
  242. #endif
  243. #ifdef CONFIG_VIDEO_MXS
  244. setup_lcd();
  245. #endif
  246. return 0;
  247. }
  248. static bool is_reva(void)
  249. {
  250. return (nxp_board_rev() == 1);
  251. }
  252. int board_late_init(void)
  253. {
  254. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  255. if (is_reva())
  256. env_set("board_rev", "REVA");
  257. #endif
  258. return 0;
  259. }
  260. int checkboard(void)
  261. {
  262. printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string());
  263. return 0;
  264. }