mx6qarm2.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <net.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <asm/arch/clock.h>
  12. #include <linux/errno.h>
  13. #include <asm/gpio.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <mmc.h>
  16. #include <fsl_esdhc_imx.h>
  17. #include <miiphy.h>
  18. #include <netdev.h>
  19. #include <usb.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  22. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  23. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  24. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  25. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  26. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  27. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  28. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  29. int dram_init(void)
  30. {
  31. #if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \
  32. defined(CONFIG_DDR_32BIT)
  33. gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2;
  34. #else
  35. gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
  36. #endif
  37. return 0;
  38. }
  39. iomux_v3_cfg_t const uart4_pads[] = {
  40. MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  41. MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  42. };
  43. iomux_v3_cfg_t const usdhc3_pads[] = {
  44. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  45. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  46. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  47. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  48. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  49. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  50. MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  51. MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  52. MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  53. MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  54. MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  55. };
  56. iomux_v3_cfg_t const usdhc4_pads[] = {
  57. MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  58. MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  59. MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  60. MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  61. MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  62. MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  63. MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  64. MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  65. MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  66. MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  67. };
  68. iomux_v3_cfg_t const enet_pads[] = {
  69. MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70. MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  75. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  76. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  78. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  79. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  80. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84. };
  85. static void setup_iomux_uart(void)
  86. {
  87. imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  88. }
  89. static void setup_iomux_enet(void)
  90. {
  91. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  92. }
  93. #ifdef CONFIG_FSL_ESDHC_IMX
  94. struct fsl_esdhc_cfg usdhc_cfg[2] = {
  95. {USDHC3_BASE_ADDR},
  96. {USDHC4_BASE_ADDR},
  97. };
  98. int board_mmc_get_env_dev(int devno)
  99. {
  100. return devno - 2;
  101. }
  102. int board_mmc_getcd(struct mmc *mmc)
  103. {
  104. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  105. int ret;
  106. if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
  107. gpio_direction_input(IMX_GPIO_NR(6, 11));
  108. ret = !gpio_get_value(IMX_GPIO_NR(6, 11));
  109. } else /* Don't have the CD GPIO pin on board */
  110. ret = 1;
  111. return ret;
  112. }
  113. int board_mmc_init(struct bd_info *bis)
  114. {
  115. int ret;
  116. u32 index = 0;
  117. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  118. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  119. for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  120. switch (index) {
  121. case 0:
  122. imx_iomux_v3_setup_multiple_pads(
  123. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  124. break;
  125. case 1:
  126. imx_iomux_v3_setup_multiple_pads(
  127. usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  128. break;
  129. default:
  130. printf("Warning: you configured more USDHC controllers"
  131. "(%d) then supported by the board (%d)\n",
  132. index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  133. return -EINVAL;
  134. }
  135. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  136. if (ret)
  137. return ret;
  138. }
  139. return 0;
  140. }
  141. #endif
  142. #define MII_MMD_ACCESS_CTRL_REG 0xd
  143. #define MII_MMD_ACCESS_ADDR_DATA_REG 0xe
  144. #define MII_DBG_PORT_REG 0x1d
  145. #define MII_DBG_PORT2_REG 0x1e
  146. int fecmxc_mii_postcall(int phy)
  147. {
  148. unsigned short val;
  149. /*
  150. * Due to the i.MX6Q Armadillo2 board HW design,there is
  151. * no 125Mhz clock input from SOC. In order to use RGMII,
  152. * We need enable AR8031 ouput a 125MHz clk from CLK_25M
  153. */
  154. miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
  155. miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
  156. miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
  157. miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
  158. val &= 0xffe3;
  159. val |= 0x18;
  160. miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
  161. /* For the RGMII phy, we need enable tx clock delay */
  162. miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
  163. miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
  164. val |= 0x0100;
  165. miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);
  166. miiphy_write("FEC", phy, MII_BMCR, 0xa100);
  167. return 0;
  168. }
  169. int board_eth_init(struct bd_info *bis)
  170. {
  171. struct eth_device *dev;
  172. int ret = cpu_eth_init(bis);
  173. if (ret)
  174. return ret;
  175. dev = eth_get_dev_by_name("FEC");
  176. if (!dev) {
  177. printf("FEC MXC: Unable to get FEC device entry\n");
  178. return -EINVAL;
  179. }
  180. ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
  181. if (ret) {
  182. printf("FEC MXC: Unable to register FEC mii postcall\n");
  183. return ret;
  184. }
  185. return 0;
  186. }
  187. #ifdef CONFIG_USB_EHCI_MX6
  188. #define USB_OTHERREGS_OFFSET 0x800
  189. #define UCTRL_PWR_POL (1 << 9)
  190. static iomux_v3_cfg_t const usb_otg_pads[] = {
  191. MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  192. MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
  193. };
  194. static void setup_usb(void)
  195. {
  196. imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
  197. ARRAY_SIZE(usb_otg_pads));
  198. /*
  199. * set daisy chain for otg_pin_id on 6q.
  200. * for 6dl, this bit is reserved
  201. */
  202. imx_iomux_set_gpr_register(1, 13, 1, 1);
  203. }
  204. int board_ehci_hcd_init(int port)
  205. {
  206. u32 *usbnc_usb_ctrl;
  207. if (port > 0)
  208. return -EINVAL;
  209. usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
  210. port * 4);
  211. setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
  212. return 0;
  213. }
  214. #endif
  215. int board_early_init_f(void)
  216. {
  217. setup_iomux_uart();
  218. setup_iomux_enet();
  219. return 0;
  220. }
  221. int board_init(void)
  222. {
  223. /* address of boot parameters */
  224. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  225. #ifdef CONFIG_USB_EHCI_MX6
  226. setup_usb();
  227. #endif
  228. return 0;
  229. }
  230. int checkboard(void)
  231. {
  232. #ifdef CONFIG_MX6DL
  233. puts("Board: MX6DL-Armadillo2\n");
  234. #else
  235. puts("Board: MX6Q-Armadillo2\n");
  236. #endif
  237. return 0;
  238. }