imximage_mx6dl.cfg 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  4. * Jason Liu <r64343@freescale.com>
  5. *
  6. * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
  7. * and create imximage boot image
  8. *
  9. * The syntax is taken as close as possible with the kwbimage
  10. */
  11. /* image version */
  12. IMAGE_VERSION 2
  13. /*
  14. * Boot Device : one of
  15. * spi, sd (the board has no nand neither onenand)
  16. */
  17. BOOT_FROM sd
  18. /*
  19. * Device Configuration Data (DCD)
  20. *
  21. * Each entry must have the format:
  22. * Addr-type Address Value
  23. *
  24. * where:
  25. * Addr-type register length (1,2 or 4 bytes)
  26. * Address absolute address of the register
  27. * value value to be stored in the register
  28. */
  29. #ifdef CONFIG_MX6DL_LPDDR2
  30. /* IOMUX SETTINGS */
  31. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
  32. DATA 4 0x020E04bc 0x00003028
  33. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
  34. DATA 4 0x020E04c0 0x00003028
  35. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
  36. DATA 4 0x020E04c4 0x00003028
  37. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
  38. DATA 4 0x020E04c8 0x00003028
  39. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
  40. DATA 4 0x020E04cc 0x00003028
  41. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
  42. DATA 4 0x020E04d0 0x00003028
  43. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
  44. DATA 4 0x020E04d4 0x00003028
  45. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
  46. DATA 4 0x020E04d8 0x00003028
  47. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
  48. DATA 4 0x020E0470 0x00000038
  49. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
  50. DATA 4 0x020E0474 0x00000038
  51. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
  52. DATA 4 0x020E0478 0x00000038
  53. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
  54. DATA 4 0x020E047c 0x00000038
  55. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
  56. DATA 4 0x020E0480 0x00000038
  57. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
  58. DATA 4 0x020E0484 0x00000038
  59. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
  60. DATA 4 0x020E0488 0x00000038
  61. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
  62. DATA 4 0x020E048c 0x00000038
  63. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
  64. DATA 4 0x020E0464 0x00000038
  65. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
  66. DATA 4 0x020E0490 0x00000038
  67. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
  68. DATA 4 0x020E04ac 0x00000038
  69. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
  70. DATA 4 0x020E04b0 0x00000038
  71. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
  72. DATA 4 0x020E0494 0x00000038
  73. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */
  74. DATA 4 0x020E04a4 0x00000038
  75. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */
  76. DATA 4 0x020E04a8 0x00000038
  77. /*
  78. * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
  79. * DSE can be configured using Group Control Register:
  80. * IOMUXC_SW_PAD_CTL_GRP_CTLDS
  81. */
  82. DATA 4 0x020E04a0 0x00000000
  83. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
  84. DATA 4 0x020E04b4 0x00000038
  85. /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
  86. DATA 4 0x020E04b8 0x00000038
  87. /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
  88. DATA 4 0x020E0764 0x00000038
  89. /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
  90. DATA 4 0x020E0770 0x00000038
  91. /* IOMUXC_SW_PAD_CTL_GRP_B2DS */
  92. DATA 4 0x020E0778 0x00000038
  93. /* IOMUXC_SW_PAD_CTL_GRP_B3DS */
  94. DATA 4 0x020E077c 0x00000038
  95. /* IOMUXC_SW_PAD_CTL_GRP_B4DS */
  96. DATA 4 0x020E0780 0x00000038
  97. /* IOMUXC_SW_PAD_CTL_GRP_B5DS */
  98. DATA 4 0x020E0784 0x00000038
  99. /* IOMUXC_SW_PAD_CTL_GRP_B6DS */
  100. DATA 4 0x020E078c 0x00000038
  101. /* IOMUXC_SW_PAD_CTL_GRP_B7DS */
  102. DATA 4 0x020E0748 0x00000038
  103. /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
  104. DATA 4 0x020E074c 0x00000038
  105. /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
  106. DATA 4 0x020E076c 0x00000038
  107. /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
  108. DATA 4 0x020E0750 0x00020000
  109. /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
  110. DATA 4 0x020E0754 0x00000000
  111. /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
  112. DATA 4 0x020E0760 0x00020000
  113. /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
  114. DATA 4 0x020E0774 0x00080000
  115. /*
  116. * DDR Controller Registers
  117. *
  118. * Manufacturer: Mocron
  119. * Device Part Number: MT42L64M64D2KH-18
  120. * Clock Freq.: 528MHz
  121. * MMDC channels: Both MMDC0, MMDC1
  122. *Density per CS in Gb: 256M
  123. * Chip Selects used: 2
  124. * Number of Banks: 8
  125. * Row address: 14
  126. * Column address: 9
  127. * Data bus width 32
  128. */
  129. /* MMDC_P0_BASE_ADDR = 0x021b0000 */
  130. /* MMDC_P1_BASE_ADDR = 0x021b4000 */
  131. /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
  132. DATA 4 0x021b001c 0x00008000
  133. /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
  134. DATA 4 0x021b401c 0x00008000
  135. /*LPDDR2 ZQ params */
  136. DATA 4 0x021b085c 0x1b5f01ff
  137. DATA 4 0x021b485c 0x1b5f01ff
  138. /* Calibration setup. */
  139. /* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */
  140. DATA 4 0x021b0800 0xa1390003
  141. /*ca bus abs delay */
  142. DATA 4 0x021b0890 0x00400000
  143. /*ca bus abs delay */
  144. DATA 4 0x021b4890 0x00400000
  145. /* values of 20,40,50,60,7f tried. no difference seen */
  146. /* DDR_PHY_P1_MPWRCADL */
  147. DATA 4 0x021b48bc 0x00055555
  148. /*frc_msr.*/
  149. DATA 4 0x021b08b8 0x00000800
  150. /*frc_msr.*/
  151. DATA 4 0x021b48b8 0x00000800
  152. /* DDR_PHY_P0_MPREDQBY0DL3 */
  153. DATA 4 0x021b081c 0x33333333
  154. /* DDR_PHY_P0_MPREDQBY1DL3 */
  155. DATA 4 0x021b0820 0x33333333
  156. /* DDR_PHY_P0_MPREDQBY2DL3 */
  157. DATA 4 0x021b0824 0x33333333
  158. /* DDR_PHY_P0_MPREDQBY3DL3 */
  159. DATA 4 0x021b0828 0x33333333
  160. /* DDR_PHY_P1_MPREDQBY0DL3 */
  161. DATA 4 0x021b481c 0x33333333
  162. /* DDR_PHY_P1_MPREDQBY1DL3 */
  163. DATA 4 0x021b4820 0x33333333
  164. /* DDR_PHY_P1_MPREDQBY2DL3 */
  165. DATA 4 0x021b4824 0x33333333
  166. /* DDR_PHY_P1_MPREDQBY3DL3 */
  167. DATA 4 0x021b4828 0x33333333
  168. /*
  169. * Read and write data delay, per byte.
  170. * For optimized DDR operation it is recommended to run mmdc_calibration
  171. * on your board, and replace 4 delay register assigns with resulted values
  172. * Note:
  173. * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
  174. * should be skipped, or the write/read calibration comming after that
  175. * will stall
  176. * b. The calibration code that runs for both MMDC0 & MMDC1 should be used.
  177. */
  178. DATA 4 0x021b0848 0x4b4b524f
  179. DATA 4 0x021b4848 0x494f4c44
  180. DATA 4 0x021b0850 0x3c3d303c
  181. DATA 4 0x021b4850 0x3c343d38
  182. /*dqs gating dis */
  183. DATA 4 0x021b083c 0x20000000
  184. DATA 4 0x021b0840 0x0
  185. DATA 4 0x021b483c 0x20000000
  186. DATA 4 0x021b4840 0x0
  187. /*clk delay */
  188. DATA 4 0x021b0858 0xa00
  189. /*clk delay */
  190. DATA 4 0x021b4858 0xa00
  191. /*frc_msr */
  192. DATA 4 0x021b08b8 0x00000800
  193. /*frc_msr */
  194. DATA 4 0x021b48b8 0x00000800
  195. /* Calibration setup end */
  196. /* Channel0 - startng address 0x80000000 */
  197. /* MMDC0_MDCFG0 */
  198. DATA 4 0x021b000c 0x34386145
  199. /* MMDC0_MDPDC */
  200. DATA 4 0x021b0004 0x00020036
  201. /* MMDC0_MDCFG1 */
  202. DATA 4 0x021b0010 0x00100c83
  203. /* MMDC0_MDCFG2 */
  204. DATA 4 0x021b0014 0x000000Dc
  205. /* MMDC0_MDMISC */
  206. DATA 4 0x021b0018 0x0000174C
  207. /* MMDC0_MDRWD;*/
  208. DATA 4 0x021b002c 0x0f9f26d2
  209. /* MMDC0_MDOR */
  210. DATA 4 0x021b0030 0x009f0e10
  211. /* MMDC0_MDCFG3LP */
  212. DATA 4 0x021b0038 0x00190778
  213. /* MMDC0_MDOTC */
  214. DATA 4 0x021b0008 0x00000000
  215. /* CS0_END */
  216. DATA 4 0x021b0040 0x0000005f
  217. /* ROC */
  218. DATA 4 0x021b0404 0x0000000f
  219. /* MMDC0_MDCTL */
  220. DATA 4 0x021b0000 0xc3010000
  221. /* Channel1 - starting address 0x10000000 */
  222. /* MMDC1_MDCFG0 */
  223. DATA 4 0x021b400c 0x34386145
  224. /* MMDC1_MDPDC */
  225. DATA 4 0x021b4004 0x00020036
  226. /* MMDC1_MDCFG1 */
  227. DATA 4 0x021b4010 0x00100c83
  228. /* MMDC1_MDCFG2 */
  229. DATA 4 0x021b4014 0x000000Dc
  230. /* MMDC1_MDMISC */
  231. DATA 4 0x021b4018 0x0000174C
  232. /* MMDC1_MDRWD;*/
  233. DATA 4 0x021b402c 0x0f9f26d2
  234. /* MMDC1_MDOR */
  235. DATA 4 0x021b4030 0x009f0e10
  236. /* MMDC1_MDCFG3LP */
  237. DATA 4 0x021b4038 0x00190778
  238. /* MMDC1_MDOTC */
  239. DATA 4 0x021b4008 0x00000000
  240. /* CS0_END */
  241. DATA 4 0x021b4040 0x0000003f
  242. /* MMDC1_MDCTL */
  243. DATA 4 0x021b4000 0xc3010000
  244. /* Channel0 : Configure DDR device:*/
  245. /* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
  246. DATA 4 0x021b001c 0x003f8030
  247. /* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
  248. DATA 4 0x021b001c 0xff0a8030
  249. /* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
  250. DATA 4 0x021b001c 0xa2018030
  251. /* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
  252. DATA 4 0x021b001c 0x06028030
  253. /* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
  254. DATA 4 0x021b001c 0x01038030
  255. /* Channel1 : Configure DDR device:*/
  256. /* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
  257. DATA 4 0x021b401c 0x003f8030
  258. /* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
  259. DATA 4 0x021b401c 0xff0a8030
  260. /* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
  261. DATA 4 0x021b401c 0xa2018030
  262. /* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
  263. DATA 4 0x021b401c 0x06028030
  264. /* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
  265. DATA 4 0x021b401c 0x01038030
  266. /* MMDC0_MDREF */
  267. DATA 4 0x021b0020 0x00005800
  268. /* MMDC1_MDREF */
  269. DATA 4 0x021b4020 0x00005800
  270. /* DDR_PHY_P0_MPODTCTRL */
  271. DATA 4 0x021b0818 0x0
  272. /* DDR_PHY_P1_MPODTCTRL */
  273. DATA 4 0x021b4818 0x0
  274. /*
  275. * calibration values based on calibration compare of 0x00ffff00:
  276. * Note, these calibration values are based on Freescale's board
  277. * May need to run calibration on target board to fine tune these
  278. */
  279. /* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */
  280. DATA 4 0x021b0800 0xa1310003
  281. /* DDR_PHY_P0_MPMUR0, frc_msr */
  282. DATA 4 0x021b08b8 0x00000800
  283. /* DDR_PHY_P1_MPMUR0, frc_msr */
  284. DATA 4 0x021b48b8 0x00000800
  285. /*
  286. * MMDC0_MDSCR, clear this register
  287. * (especially the configuration bit as initialization is complete)
  288. */
  289. DATA 4 0x021b001c 0x00000000
  290. /*
  291. * MMDC0_MDSCR, clear this register
  292. * (especially the configuration bit as initialization is complete)
  293. */
  294. DATA 4 0x021b401c 0x00000000
  295. DATA 4 0x020c4068 0x00C03F3F
  296. DATA 4 0x020c406c 0x0030FC03
  297. DATA 4 0x020c4070 0x0FFFC000
  298. DATA 4 0x020c4074 0x3FF00000
  299. DATA 4 0x020c4078 0x00FFF300
  300. DATA 4 0x020c407c 0x0F0000C3
  301. DATA 4 0x020c4080 0x000003FF
  302. DATA 4 0x020e0010 0xF00000CF
  303. DATA 4 0x020e0018 0x007F007F
  304. DATA 4 0x020e001c 0x007F007F
  305. #else /* CONFIG_MX6DL_LPDDR2 */
  306. DATA 4 0x020e0798 0x000c0000
  307. DATA 4 0x020e0758 0x00000000
  308. DATA 4 0x020e0588 0x00000030
  309. DATA 4 0x020e0594 0x00000030
  310. DATA 4 0x020e056c 0x00000030
  311. DATA 4 0x020e0578 0x00000030
  312. DATA 4 0x020e074c 0x00000030
  313. DATA 4 0x020e057c 0x00000030
  314. DATA 4 0x020e0590 0x00003000
  315. DATA 4 0x020e0598 0x00003000
  316. DATA 4 0x020e058c 0x00000000
  317. DATA 4 0x020e059c 0x00003030
  318. DATA 4 0x020e05a0 0x00003030
  319. DATA 4 0x020e078c 0x00000030
  320. DATA 4 0x020e0750 0x00020000
  321. DATA 4 0x020e05a8 0x00000030
  322. DATA 4 0x020e05b0 0x00000030
  323. DATA 4 0x020e0524 0x00000030
  324. DATA 4 0x020e051c 0x00000030
  325. DATA 4 0x020e0518 0x00000030
  326. DATA 4 0x020e050c 0x00000030
  327. DATA 4 0x020e05b8 0x00000030
  328. DATA 4 0x020e05c0 0x00000030
  329. DATA 4 0x020e0774 0x00020000
  330. DATA 4 0x020e0784 0x00000030
  331. DATA 4 0x020e0788 0x00000030
  332. DATA 4 0x020e0794 0x00000030
  333. DATA 4 0x020e079c 0x00000030
  334. DATA 4 0x020e07a0 0x00000030
  335. DATA 4 0x020e07a4 0x00000030
  336. DATA 4 0x020e07a8 0x00000030
  337. DATA 4 0x020e0748 0x00000030
  338. DATA 4 0x020e05ac 0x00000030
  339. DATA 4 0x020e05b4 0x00000030
  340. DATA 4 0x020e0528 0x00000030
  341. DATA 4 0x020e0520 0x00000030
  342. DATA 4 0x020e0514 0x00000030
  343. DATA 4 0x020e0510 0x00000030
  344. DATA 4 0x020e05bc 0x00000030
  345. DATA 4 0x020e05c4 0x00000030
  346. DATA 4 0x021b0800 0xa1390003
  347. DATA 4 0x021b4800 0xa1390003
  348. DATA 4 0x021b080c 0x001F001F
  349. DATA 4 0x021b0810 0x001F001F
  350. DATA 4 0x021b480c 0x00370037
  351. DATA 4 0x021b4810 0x00370037
  352. DATA 4 0x021b083c 0x422f0220
  353. DATA 4 0x021b0840 0x021f0219
  354. DATA 4 0x021b483C 0x422f0220
  355. DATA 4 0x021b4840 0x022d022f
  356. DATA 4 0x021b0848 0x47494b49
  357. DATA 4 0x021b4848 0x48484c47
  358. DATA 4 0x021b0850 0x39382b2f
  359. DATA 4 0x021b4850 0x2f35312c
  360. DATA 4 0x021b081c 0x33333333
  361. DATA 4 0x021b0820 0x33333333
  362. DATA 4 0x021b0824 0x33333333
  363. DATA 4 0x021b0828 0x33333333
  364. DATA 4 0x021b481c 0x33333333
  365. DATA 4 0x021b4820 0x33333333
  366. DATA 4 0x021b4824 0x33333333
  367. DATA 4 0x021b4828 0x33333333
  368. DATA 4 0x021b08b8 0x00000800
  369. DATA 4 0x021b48b8 0x00000800
  370. DATA 4 0x021b0004 0x0002002d
  371. DATA 4 0x021b0008 0x00333030
  372. DATA 4 0x021b000c 0x40445323
  373. DATA 4 0x021b0010 0xb66e8c63
  374. DATA 4 0x021b0014 0x01ff00db
  375. DATA 4 0x021b0018 0x00081740
  376. DATA 4 0x021b001c 0x00008000
  377. DATA 4 0x021b002c 0x000026d2
  378. DATA 4 0x021b0030 0x00440e21
  379. #ifdef CONFIG_DDR_32BIT
  380. DATA 4 0x021b0040 0x00000017
  381. DATA 4 0x021b0000 0xc3190000
  382. #else
  383. DATA 4 0x021b0040 0x00000027
  384. DATA 4 0x021b0000 0xc31a0000
  385. #endif
  386. DATA 4 0x021b001c 0x04008032
  387. DATA 4 0x021b001c 0x0400803a
  388. DATA 4 0x021b001c 0x00008033
  389. DATA 4 0x021b001c 0x0000803b
  390. DATA 4 0x021b001c 0x00428031
  391. DATA 4 0x021b001c 0x00428039
  392. DATA 4 0x021b001c 0x07208030
  393. DATA 4 0x021b001c 0x07208038
  394. DATA 4 0x021b001c 0x04008040
  395. DATA 4 0x021b001c 0x04008048
  396. DATA 4 0x021b0020 0x00005800
  397. DATA 4 0x021b0818 0x00000007
  398. DATA 4 0x021b4818 0x00000007
  399. DATA 4 0x021b0004 0x0002556d
  400. DATA 4 0x021b4004 0x00011006
  401. DATA 4 0x021b001c 0x00000000
  402. DATA 4 0x020c4068 0x00C03F3F
  403. DATA 4 0x020c406c 0x0030FC03
  404. DATA 4 0x020c4070 0x0FFFC000
  405. DATA 4 0x020c4074 0x3FF00000
  406. DATA 4 0x020c4078 0x00FFF300
  407. DATA 4 0x020c407c 0x0F0000C3
  408. DATA 4 0x020c4080 0x000003FF
  409. DATA 4 0x020e0010 0xF00000CF
  410. DATA 4 0x020e0018 0x007F007F
  411. DATA 4 0x020e001c 0x007F007F
  412. #endif /* CONFIG_MX6DL_LPDDR2 */