mx35pdk.c 7.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
  4. *
  5. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <net.h>
  10. #include <asm/io.h>
  11. #include <linux/delay.h>
  12. #include <linux/errno.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/crm_regs.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/iomux-mx35.h>
  17. #include <i2c.h>
  18. #include <power/pmic.h>
  19. #include <fsl_pmic.h>
  20. #include <mmc.h>
  21. #include <fsl_esdhc_imx.h>
  22. #include <mc9sdz60.h>
  23. #include <mc13892.h>
  24. #include <linux/types.h>
  25. #include <asm/gpio.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <netdev.h>
  28. #include <asm/mach-types.h>
  29. #ifndef CONFIG_BOARD_LATE_INIT
  30. #error "CONFIG_BOARD_LATE_INIT must be set for this board"
  31. #endif
  32. #ifndef CONFIG_BOARD_EARLY_INIT_F
  33. #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
  34. #endif
  35. DECLARE_GLOBAL_DATA_PTR;
  36. int dram_init(void)
  37. {
  38. u32 size1, size2;
  39. size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  40. size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  41. gd->ram_size = size1 + size2;
  42. return 0;
  43. }
  44. int dram_init_banksize(void)
  45. {
  46. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  47. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  48. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  49. gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  50. return 0;
  51. }
  52. #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
  53. static void setup_iomux_i2c(void)
  54. {
  55. static const iomux_v3_cfg_t i2c1_pads[] = {
  56. NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
  57. NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
  58. };
  59. /* setup pins for I2C1 */
  60. imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
  61. }
  62. static void setup_iomux_spi(void)
  63. {
  64. static const iomux_v3_cfg_t spi_pads[] = {
  65. MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
  66. MX35_PAD_CSPI1_MISO__CSPI1_MISO,
  67. MX35_PAD_CSPI1_SS0__CSPI1_SS0,
  68. MX35_PAD_CSPI1_SS1__CSPI1_SS1,
  69. MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
  70. };
  71. imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
  72. }
  73. #define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
  74. PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
  75. #define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
  76. static void setup_iomux_usbotg(void)
  77. {
  78. static const iomux_v3_cfg_t usbotg_pads[] = {
  79. NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
  80. USBOTG_OUT_PAD_CTRL),
  81. NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
  82. USBOTG_IN_PAD_CTRL),
  83. };
  84. /* Set up pins for USBOTG. */
  85. imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
  86. }
  87. #define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
  88. static void setup_iomux_fec(void)
  89. {
  90. static const iomux_v3_cfg_t fec_pads[] = {
  91. NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |
  92. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  93. NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |
  94. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  95. NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |
  96. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  97. NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |
  98. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  99. NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |
  100. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  101. NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
  102. NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
  103. NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
  104. NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |
  105. PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
  106. NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
  107. NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |
  108. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  109. NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |
  110. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  111. NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |
  112. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  113. NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
  114. NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |
  115. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  116. NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
  117. NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |
  118. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  119. NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
  120. };
  121. /* setup pins for FEC */
  122. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  123. }
  124. int board_early_init_f(void)
  125. {
  126. struct ccm_regs *ccm =
  127. (struct ccm_regs *)IMX_CCM_BASE;
  128. /* enable clocks */
  129. writel(readl(&ccm->cgr0) |
  130. MXC_CCM_CGR0_EMI_MASK |
  131. MXC_CCM_CGR0_EDIO_MASK |
  132. MXC_CCM_CGR0_EPIT1_MASK,
  133. &ccm->cgr0);
  134. writel(readl(&ccm->cgr1) |
  135. MXC_CCM_CGR1_FEC_MASK |
  136. MXC_CCM_CGR1_GPIO1_MASK |
  137. MXC_CCM_CGR1_GPIO2_MASK |
  138. MXC_CCM_CGR1_GPIO3_MASK |
  139. MXC_CCM_CGR1_I2C1_MASK |
  140. MXC_CCM_CGR1_I2C2_MASK |
  141. MXC_CCM_CGR1_IPU_MASK,
  142. &ccm->cgr1);
  143. /* Setup NAND */
  144. __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
  145. setup_iomux_i2c();
  146. setup_iomux_usbotg();
  147. setup_iomux_fec();
  148. setup_iomux_spi();
  149. return 0;
  150. }
  151. int board_init(void)
  152. {
  153. gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
  154. /* address of boot parameters */
  155. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  156. return 0;
  157. }
  158. static inline int pmic_detect(void)
  159. {
  160. unsigned int id;
  161. struct pmic *p = pmic_get("FSL_PMIC");
  162. if (!p)
  163. return -ENODEV;
  164. pmic_reg_read(p, REG_IDENTIFICATION, &id);
  165. id = (id >> 6) & 0x7;
  166. if (id == 0x7)
  167. return 1;
  168. return 0;
  169. }
  170. u32 get_board_rev(void)
  171. {
  172. int rev;
  173. rev = pmic_detect();
  174. return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  175. }
  176. int board_late_init(void)
  177. {
  178. u8 val;
  179. u32 pmic_val;
  180. struct pmic *p;
  181. int ret;
  182. ret = pmic_init(I2C_0);
  183. if (ret)
  184. return ret;
  185. if (pmic_detect()) {
  186. p = pmic_get("FSL_PMIC");
  187. imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);
  188. pmic_reg_read(p, REG_SETTING_0, &pmic_val);
  189. pmic_reg_write(p, REG_SETTING_0,
  190. pmic_val | VO_1_30V | VO_1_50V);
  191. pmic_reg_read(p, REG_MODE_0, &pmic_val);
  192. pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
  193. imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);
  194. gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
  195. }
  196. val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
  197. mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
  198. mdelay(200);
  199. val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
  200. mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
  201. mdelay(200);
  202. val |= 0x80;
  203. mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
  204. /* Print board revision */
  205. printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
  206. return 0;
  207. }
  208. int board_eth_init(struct bd_info *bis)
  209. {
  210. #if defined(CONFIG_SMC911X)
  211. int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  212. if (rc)
  213. return rc;
  214. #endif
  215. return cpu_eth_init(bis);
  216. }
  217. #if defined(CONFIG_FSL_ESDHC_IMX)
  218. struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
  219. int board_mmc_init(struct bd_info *bis)
  220. {
  221. static const iomux_v3_cfg_t sdhc1_pads[] = {
  222. MX35_PAD_SD1_CMD__ESDHC1_CMD,
  223. MX35_PAD_SD1_CLK__ESDHC1_CLK,
  224. MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
  225. MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
  226. MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
  227. MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
  228. };
  229. /* configure pins for SDHC1 only */
  230. imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
  231. esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  232. return fsl_esdhc_initialize(bis, &esdhc_cfg);
  233. }
  234. int board_mmc_getcd(struct mmc *mmc)
  235. {
  236. return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
  237. }
  238. #endif