tlb.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008-2010 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2000
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. */
  8. #include <common.h>
  9. #include <asm/mmu.h>
  10. struct fsl_e_tlb_entry tlb_table[] = {
  11. /* TLB 0 - for temp stack in cache */
  12. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  13. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  14. 0, 0, BOOKE_PAGESZ_4K, 0),
  15. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  16. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  17. 0, 0, BOOKE_PAGESZ_4K, 0),
  18. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  19. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  20. 0, 0, BOOKE_PAGESZ_4K, 0),
  21. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  22. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  23. 0, 0, BOOKE_PAGESZ_4K, 0),
  24. /* TLB 1 */
  25. /* *I*** - Covers boot page */
  26. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  27. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  28. 0, 0, BOOKE_PAGESZ_4K, 1),
  29. /* *I*G* - CCSRBAR */
  30. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  31. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  32. 0, 1, BOOKE_PAGESZ_1M, 1),
  33. /* W**G* - Flash/promjet, localbus */
  34. /* This will be changed to *I*G* after relocation to RAM. */
  35. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  36. MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  37. 0, 2, BOOKE_PAGESZ_256M, 1),
  38. #ifndef CONFIG_NAND_SPL
  39. /* *I*G* - PCI */
  40. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
  41. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  42. 0, 3, BOOKE_PAGESZ_1G, 1),
  43. /* *I*G* - PCI */
  44. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
  45. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  46. 0, 4, BOOKE_PAGESZ_256M, 1),
  47. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
  48. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  49. 0, 5, BOOKE_PAGESZ_256M, 1),
  50. /* *I*G* - PCI I/O */
  51. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
  52. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  53. 0, 6, BOOKE_PAGESZ_256K, 1),
  54. #endif
  55. /* *I*G - NAND */
  56. SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  57. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  58. 0, 7, BOOKE_PAGESZ_1M, 1),
  59. SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
  60. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  61. 0, 8, BOOKE_PAGESZ_4K, 1),
  62. #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
  63. /* *I*G - L2SRAM */
  64. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR,
  65. CONFIG_SYS_INIT_L2_ADDR_PHYS,
  66. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  67. 0, 9, BOOKE_PAGESZ_256K, 1),
  68. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
  69. CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
  70. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  71. 0, 10, BOOKE_PAGESZ_256K, 1),
  72. #endif
  73. };
  74. int num_tlb_entries = ARRAY_SIZE(tlb_table);