mpc8572ds.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <image.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <net.h>
  12. #include <pci.h>
  13. #include <asm/processor.h>
  14. #include <asm/mmu.h>
  15. #include <asm/cache.h>
  16. #include <asm/immap_85xx.h>
  17. #include <asm/fsl_pci.h>
  18. #include <fsl_ddr_sdram.h>
  19. #include <asm/io.h>
  20. #include <asm/fsl_serdes.h>
  21. #include <miiphy.h>
  22. #include <linux/delay.h>
  23. #include <linux/libfdt.h>
  24. #include <fdt_support.h>
  25. #include <tsec.h>
  26. #include <fsl_mdio.h>
  27. #include <netdev.h>
  28. #include "../common/sgmii_riser.h"
  29. int checkboard (void)
  30. {
  31. u8 vboot;
  32. u8 *pixis_base = (u8 *)PIXIS_BASE;
  33. printf("Board: MPC8572DS Sys ID: 0x%02x, "
  34. "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  35. in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  36. in_8(pixis_base + PIXIS_PVER));
  37. vboot = in_8(pixis_base + PIXIS_VBOOT);
  38. switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
  39. case PIXIS_VBOOT_LBMAP_NOR0:
  40. puts ("vBank: 0\n");
  41. break;
  42. case PIXIS_VBOOT_LBMAP_PJET:
  43. puts ("Promjet\n");
  44. break;
  45. case PIXIS_VBOOT_LBMAP_NAND:
  46. puts ("NAND\n");
  47. break;
  48. case PIXIS_VBOOT_LBMAP_NOR1:
  49. puts ("vBank: 1\n");
  50. break;
  51. }
  52. return 0;
  53. }
  54. #if !defined(CONFIG_SPD_EEPROM)
  55. /*
  56. * Fixed sdram init -- doesn't use serial presence detect.
  57. */
  58. phys_size_t fixed_sdram (void)
  59. {
  60. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  61. struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
  62. uint d_init;
  63. ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  64. ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  65. ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  66. ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  67. ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  68. ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  69. ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  70. ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  71. ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  72. ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  73. ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  74. ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
  75. #if defined (CONFIG_DDR_ECC)
  76. ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
  77. ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
  78. ddr->err_sbe = CONFIG_SYS_DDR_SBE;
  79. #endif
  80. asm("sync;isync");
  81. udelay(500);
  82. ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
  83. #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  84. d_init = 1;
  85. debug("DDR - 1st controller: memory initializing\n");
  86. /*
  87. * Poll until memory is initialized.
  88. * 512 Meg at 400 might hit this 200 times or so.
  89. */
  90. while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
  91. udelay(1000);
  92. }
  93. debug("DDR: memory initialized\n\n");
  94. asm("sync; isync");
  95. udelay(500);
  96. #endif
  97. return 512 * 1024 * 1024;
  98. }
  99. #endif
  100. #ifdef CONFIG_PCI
  101. void pci_init_board(void)
  102. {
  103. struct pci_controller *hose;
  104. fsl_pcie_init_board(0);
  105. hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
  106. if (hose) {
  107. u32 temp32;
  108. u8 uli_busno = hose->first_busno + 2;
  109. /*
  110. * Activate ULI1575 legacy chip by performing a fake
  111. * memory access. Needed to make ULI RTC work.
  112. * Device 1d has the first on-board memory BAR.
  113. */
  114. pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
  115. PCI_BASE_ADDRESS_1, &temp32);
  116. if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
  117. void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
  118. temp32, 4, 0);
  119. debug(" uli1572 read to %p\n", p);
  120. in_be32(p);
  121. }
  122. }
  123. }
  124. #endif
  125. int board_early_init_r(void)
  126. {
  127. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  128. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  129. /*
  130. * Remap Boot flash + PROMJET region to caching-inhibited
  131. * so that flash can be erased properly.
  132. */
  133. /* Flush d-cache and invalidate i-cache of any FLASH data */
  134. flush_dcache();
  135. invalidate_icache();
  136. if (flash_esel == -1) {
  137. /* very unlikely unless something is messed up */
  138. puts("Error: Could not find TLB for FLASH BASE\n");
  139. flash_esel = 2; /* give our best effort to continue */
  140. } else {
  141. /* invalidate existing TLB entry for flash + promjet */
  142. disable_tlb(flash_esel);
  143. }
  144. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  145. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
  146. 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
  147. return 0;
  148. }
  149. int board_eth_init(struct bd_info *bis)
  150. {
  151. #ifdef CONFIG_TSEC_ENET
  152. struct fsl_pq_mdio_info mdio_info;
  153. struct tsec_info_struct tsec_info[4];
  154. int num = 0;
  155. #ifdef CONFIG_TSEC1
  156. SET_STD_TSEC_INFO(tsec_info[num], 1);
  157. if (is_serdes_configured(SGMII_TSEC1)) {
  158. puts("eTSEC1 is in sgmii mode.\n");
  159. tsec_info[num].flags |= TSEC_SGMII;
  160. }
  161. num++;
  162. #endif
  163. #ifdef CONFIG_TSEC2
  164. SET_STD_TSEC_INFO(tsec_info[num], 2);
  165. if (is_serdes_configured(SGMII_TSEC2)) {
  166. puts("eTSEC2 is in sgmii mode.\n");
  167. tsec_info[num].flags |= TSEC_SGMII;
  168. }
  169. num++;
  170. #endif
  171. #ifdef CONFIG_TSEC3
  172. SET_STD_TSEC_INFO(tsec_info[num], 3);
  173. if (is_serdes_configured(SGMII_TSEC3)) {
  174. puts("eTSEC3 is in sgmii mode.\n");
  175. tsec_info[num].flags |= TSEC_SGMII;
  176. }
  177. num++;
  178. #endif
  179. #ifdef CONFIG_TSEC4
  180. SET_STD_TSEC_INFO(tsec_info[num], 4);
  181. if (is_serdes_configured(SGMII_TSEC4)) {
  182. puts("eTSEC4 is in sgmii mode.\n");
  183. tsec_info[num].flags |= TSEC_SGMII;
  184. }
  185. num++;
  186. #endif
  187. if (!num) {
  188. printf("No TSECs initialized\n");
  189. return 0;
  190. }
  191. #ifdef CONFIG_FSL_SGMII_RISER
  192. fsl_sgmii_riser_init(tsec_info, num);
  193. #endif
  194. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  195. mdio_info.name = DEFAULT_MII_NAME;
  196. fsl_pq_mdio_init(bis, &mdio_info);
  197. tsec_eth_init(bis, tsec_info, num);
  198. #endif
  199. return pci_eth_init(bis);
  200. }
  201. #if defined(CONFIG_OF_BOARD_SETUP)
  202. int ft_board_setup(void *blob, struct bd_info *bd)
  203. {
  204. phys_addr_t base;
  205. phys_size_t size;
  206. ft_cpu_setup(blob, bd);
  207. base = env_get_bootm_low();
  208. size = env_get_bootm_size();
  209. fdt_fixup_memory(blob, (u64)base, (u64)size);
  210. FT_FSL_PCI_SETUP;
  211. #ifdef CONFIG_FSL_SGMII_RISER
  212. fsl_sgmii_riser_fdt_fixup(blob);
  213. #endif
  214. return 0;
  215. }
  216. #endif