ddr.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2008 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fsl_ddr_sdram.h>
  7. #include <fsl_ddr_dimm_params.h>
  8. struct board_specific_parameters {
  9. u32 n_ranks;
  10. u32 datarate_mhz_high;
  11. u32 clk_adjust;
  12. u32 cpo;
  13. u32 write_data_delay;
  14. u32 force_2t;
  15. };
  16. /*
  17. * This table contains all valid speeds we want to override with board
  18. * specific parameters. datarate_mhz_high values need to be in ascending order
  19. * for each n_ranks group.
  20. *
  21. * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
  22. * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
  23. * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
  24. * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
  25. * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
  26. *
  27. * CPO value doesn't matter if workaround for errata 111 and 134 enabled.
  28. */
  29. static const struct board_specific_parameters udimm0[] = {
  30. /*
  31. * memory controller 0
  32. * num| hi| clk| cpo|wrdata|2T
  33. * ranks| mhz|adjst| | delay|
  34. */
  35. {2, 333, 8, 7, 5, 0},
  36. {2, 400, 8, 9, 5, 0},
  37. {2, 549, 8, 11, 5, 0},
  38. {2, 680, 8, 10, 5, 0},
  39. {2, 850, 8, 12, 5, 1},
  40. {1, 333, 6, 7, 3, 0},
  41. {1, 400, 6, 9, 3, 0},
  42. {1, 549, 6, 11, 3, 0},
  43. {1, 680, 1, 10, 5, 0},
  44. {1, 850, 1, 12, 5, 0},
  45. {}
  46. };
  47. static const struct board_specific_parameters udimm1[] = {
  48. /*
  49. * memory controller 1
  50. * num| hi| clk| cpo|wrdata|2T
  51. * ranks| mhz|adjst| | delay|
  52. */
  53. {2, 333, 8, 7, 5, 0},
  54. {2, 400, 8, 9, 5, 0},
  55. {2, 549, 8, 11, 5, 0},
  56. {2, 680, 8, 11, 5, 0},
  57. {2, 850, 8, 13, 5, 1},
  58. {1, 333, 6, 7, 3, 0},
  59. {1, 400, 6, 9, 3, 0},
  60. {1, 549, 6, 11, 3, 0},
  61. {1, 680, 1, 11, 6, 0},
  62. {1, 850, 1, 13, 6, 0},
  63. {}
  64. };
  65. static const struct board_specific_parameters *udimms[] = {
  66. udimm0,
  67. udimm1,
  68. };
  69. static const struct board_specific_parameters rdimm0[] = {
  70. /*
  71. * memory controller 0
  72. * num| hi| clk| cpo|wrdata|2T
  73. * ranks| mhz|adjst| | delay|
  74. */
  75. {2, 333, 4, 7, 3, 0},
  76. {2, 400, 4, 9, 3, 0},
  77. {2, 549, 4, 11, 3, 0},
  78. {2, 680, 4, 10, 3, 0},
  79. {2, 850, 4, 12, 3, 1},
  80. {}
  81. };
  82. static const struct board_specific_parameters rdimm1[] = {
  83. /*
  84. * memory controller 1
  85. * num| hi| clk| cpo|wrdata|2T
  86. * ranks| mhz|adjst| | delay|
  87. */
  88. {2, 333, 4, 7, 3, 0},
  89. {2, 400, 4, 9, 3, 0},
  90. {2, 549, 4, 11, 3, 0},
  91. {2, 680, 4, 11, 3, 0},
  92. {2, 850, 4, 13, 3, 1},
  93. {}
  94. };
  95. static const struct board_specific_parameters *rdimms[] = {
  96. rdimm0,
  97. rdimm1,
  98. };
  99. void fsl_ddr_board_options(memctl_options_t *popts,
  100. dimm_params_t *pdimm,
  101. unsigned int ctrl_num)
  102. {
  103. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  104. ulong ddr_freq;
  105. if (ctrl_num > 1) {
  106. printf("Wrong parameter for controller number %d", ctrl_num);
  107. return;
  108. }
  109. if (!pdimm->n_ranks)
  110. return;
  111. if (popts->registered_dimm_en)
  112. pbsp = rdimms[ctrl_num];
  113. else
  114. pbsp = udimms[ctrl_num];
  115. /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  116. * freqency and n_banks specified in board_specific_parameters table.
  117. */
  118. ddr_freq = get_ddr_freq(0) / 1000000;
  119. while (pbsp->datarate_mhz_high) {
  120. if (pbsp->n_ranks == pdimm->n_ranks) {
  121. if (ddr_freq <= pbsp->datarate_mhz_high) {
  122. popts->clk_adjust = pbsp->clk_adjust;
  123. popts->cpo_override = pbsp->cpo;
  124. popts->write_data_delay =
  125. pbsp->write_data_delay;
  126. popts->twot_en = pbsp->force_2t;
  127. goto found;
  128. }
  129. pbsp_highest = pbsp;
  130. }
  131. pbsp++;
  132. }
  133. if (pbsp_highest) {
  134. printf("Error: board specific timing not found "
  135. "for data rate %lu MT/s!\n"
  136. "Trying to use the highest speed (%u) parameters\n",
  137. ddr_freq, pbsp_highest->datarate_mhz_high);
  138. popts->clk_adjust = pbsp->clk_adjust;
  139. popts->cpo_override = pbsp->cpo;
  140. popts->write_data_delay = pbsp->write_data_delay;
  141. popts->twot_en = pbsp->force_2t;
  142. } else {
  143. panic("DIMM is not supported by this board");
  144. }
  145. found:
  146. /*
  147. * Factors to consider for half-strength driver enable:
  148. * - number of DIMMs installed
  149. */
  150. popts->half_strength_driver_enable = 0;
  151. }