tlb.c 2.9 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2000
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. */
  8. #include <common.h>
  9. #include <asm/mmu.h>
  10. struct fsl_e_tlb_entry tlb_table[] = {
  11. /* TLB 0 - for temp stack in cache */
  12. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  13. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  14. 0, 0, BOOKE_PAGESZ_4K, 0),
  15. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  16. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  17. 0, 0, BOOKE_PAGESZ_4K, 0),
  18. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  19. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  20. 0, 0, BOOKE_PAGESZ_4K, 0),
  21. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  22. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  23. 0, 0, BOOKE_PAGESZ_4K, 0),
  24. /*
  25. * TLB 0: 16M Non-cacheable, guarded
  26. * 0xff000000 16M FLASH
  27. * Out of reset this entry is only 4K.
  28. */
  29. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
  30. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  31. 0, 0, BOOKE_PAGESZ_16M, 1),
  32. /*
  33. * TLB 1: 256M Non-cacheable, guarded
  34. * 0x80000000 256M PCI1 MEM First half
  35. */
  36. SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
  37. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  38. 0, 1, BOOKE_PAGESZ_256M, 1),
  39. /*
  40. * TLB 2: 256M Non-cacheable, guarded
  41. * 0x90000000 256M PCI1 MEM Second half
  42. */
  43. SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
  44. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  45. 0, 2, BOOKE_PAGESZ_256M, 1),
  46. /*
  47. * TLB 3: 256M Non-cacheable, guarded
  48. * 0xa0000000 256M PCI2 MEM First half
  49. */
  50. SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
  51. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  52. 0, 3, BOOKE_PAGESZ_256M, 1),
  53. /*
  54. * TLB 4: 256M Non-cacheable, guarded
  55. * 0xb0000000 256M PCI2 MEM Second half
  56. */
  57. SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
  58. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  59. 0, 4, BOOKE_PAGESZ_256M, 1),
  60. /*
  61. * TLB 5: 64M Non-cacheable, guarded
  62. * 0xe000_0000 1M CCSRBAR
  63. * 0xe200_0000 16M PCI1 IO
  64. * 0xe300_0000 16M PCI2 IO
  65. */
  66. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  67. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  68. 0, 5, BOOKE_PAGESZ_64M, 1),
  69. /*
  70. * TLB 6: 64M Cacheable, non-guarded
  71. * 0xf000_0000 64M LBC SDRAM
  72. */
  73. SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
  74. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  75. 0, 6, BOOKE_PAGESZ_64M, 1),
  76. /*
  77. * TLB 7: 1M Non-cacheable, guarded
  78. * 0xf8000000 1M CADMUS registers
  79. */
  80. SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
  81. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  82. 0, 7, BOOKE_PAGESZ_1M, 1),
  83. };
  84. int num_tlb_entries = ARRAY_SIZE(tlb_table);