mpc8541cds.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2004, 2011 Freescale Semiconductor.
  4. *
  5. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <pci.h>
  10. #include <vsprintf.h>
  11. #include <asm/processor.h>
  12. #include <asm/mmu.h>
  13. #include <asm/immap_85xx.h>
  14. #include <fsl_ddr_sdram.h>
  15. #include <ioports.h>
  16. #include <spd_sdram.h>
  17. #include <linux/delay.h>
  18. #include <linux/libfdt.h>
  19. #include <fdt_support.h>
  20. #include "../common/cadmus.h"
  21. #include "../common/eeprom.h"
  22. #include "../common/via.h"
  23. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  24. extern void ddr_enable_ecc(unsigned int dram_size);
  25. #endif
  26. void local_bus_init(void);
  27. /*
  28. * I/O Port configuration table
  29. *
  30. * if conf is 1, then that port pin will be configured at boot time
  31. * according to the five values podr/pdir/ppar/psor/pdat for that entry
  32. */
  33. const iop_conf_t iop_conf_tab[4][32] = {
  34. /* Port A configuration */
  35. { /* conf ppar psor pdir podr pdat */
  36. /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
  37. /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
  38. /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
  39. /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
  40. /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
  41. /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
  42. /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
  43. /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
  44. /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
  45. /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
  46. /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
  47. /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
  48. /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
  49. /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
  50. /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
  51. /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
  52. /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
  53. /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
  54. /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
  55. /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
  56. /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
  57. /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
  58. /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
  59. /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
  60. /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
  61. /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
  62. /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
  63. /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
  64. /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
  65. /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
  66. /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
  67. /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
  68. },
  69. /* Port B configuration */
  70. { /* conf ppar psor pdir podr pdat */
  71. /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
  72. /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
  73. /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
  74. /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
  75. /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
  76. /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
  77. /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
  78. /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
  79. /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
  80. /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
  81. /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
  82. /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
  83. /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
  84. /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
  85. /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
  86. /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
  87. /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
  88. /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
  89. /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
  90. /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
  91. /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  92. /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  93. /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  94. /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  95. /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  96. /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  97. /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  98. /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  99. /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  100. /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  101. /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  102. /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  103. },
  104. /* Port C */
  105. { /* conf ppar psor pdir podr pdat */
  106. /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
  107. /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
  108. /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
  109. /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
  110. /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
  111. /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
  112. /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
  113. /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
  114. /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
  115. /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
  116. /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
  117. /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
  118. /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
  119. /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
  120. /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
  121. /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
  122. /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
  123. /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
  124. /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
  125. /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
  126. /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
  127. /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
  128. /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
  129. /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
  130. /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
  131. /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
  132. /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
  133. /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
  134. /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
  135. /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
  136. /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
  137. /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
  138. },
  139. /* Port D */
  140. { /* conf ppar psor pdir podr pdat */
  141. /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
  142. /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
  143. /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
  144. /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
  145. /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
  146. /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
  147. /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
  148. /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
  149. /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
  150. /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
  151. /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
  152. /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
  153. /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
  154. /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
  155. /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
  156. /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
  157. /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
  158. /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
  159. /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
  160. /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
  161. /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
  162. /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
  163. /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
  164. /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
  165. /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
  166. /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
  167. /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
  168. /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
  169. /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  170. /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  171. /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  172. /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  173. }
  174. };
  175. int checkboard (void)
  176. {
  177. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  178. char buf[32];
  179. /* PCI slot in USER bits CSR[6:7] by convention. */
  180. uint pci_slot = get_pci_slot ();
  181. uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
  182. uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
  183. uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
  184. uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
  185. uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
  186. uint cpu_board_rev = get_cpu_board_revision ();
  187. printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
  188. get_board_version (), pci_slot);
  189. printf ("CPU Board Revision %d.%d (0x%04x)\n",
  190. MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
  191. MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
  192. printf("PCI1: %d bit, %s MHz, %s\n",
  193. (pci1_32) ? 32 : 64,
  194. strmhz(buf, pci1_speed),
  195. pci1_clk_sel ? "sync" : "async");
  196. if (pci_dual) {
  197. printf("PCI2: 32 bit, 66 MHz, %s\n",
  198. pci2_clk_sel ? "sync" : "async");
  199. } else {
  200. printf("PCI2: disabled\n");
  201. }
  202. /*
  203. * Initialize local bus.
  204. */
  205. local_bus_init ();
  206. return 0;
  207. }
  208. /*
  209. * Initialize Local Bus
  210. */
  211. void
  212. local_bus_init(void)
  213. {
  214. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  215. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  216. uint clkdiv;
  217. uint lbc_hz;
  218. sys_info_t sysinfo;
  219. uint temp_lbcdll;
  220. /*
  221. * Errata LBC11.
  222. * Fix Local Bus clock glitch when DLL is enabled.
  223. *
  224. * If localbus freq is < 66MHz, DLL bypass mode must be used.
  225. * If localbus freq is > 133MHz, DLL can be safely enabled.
  226. * Between 66 and 133, the DLL is enabled with an override workaround.
  227. */
  228. get_sys_info(&sysinfo);
  229. clkdiv = lbc->lcrr & LCRR_CLKDIV;
  230. lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
  231. if (lbc_hz < 66) {
  232. lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
  233. } else if (lbc_hz >= 133) {
  234. lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
  235. } else {
  236. lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
  237. udelay(200);
  238. /*
  239. * Sample LBC DLL ctrl reg, upshift it to set the
  240. * override bits.
  241. */
  242. temp_lbcdll = gur->lbcdllcr;
  243. gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
  244. asm("sync;isync;msync");
  245. }
  246. }
  247. /*
  248. * Initialize SDRAM memory on the Local Bus.
  249. */
  250. void lbc_sdram_init(void)
  251. {
  252. #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
  253. uint idx;
  254. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  255. uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
  256. uint cpu_board_rev;
  257. uint lsdmr_common;
  258. puts("LBC SDRAM: ");
  259. print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
  260. "\n ");
  261. /*
  262. * Setup SDRAM Base and Option Registers
  263. */
  264. set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  265. set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
  266. lbc->lbcr = CONFIG_SYS_LBC_LBCR;
  267. asm("msync");
  268. lbc->lsrt = CONFIG_SYS_LBC_LSRT;
  269. lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
  270. asm("msync");
  271. /*
  272. * Determine which address lines to use baed on CPU board rev.
  273. */
  274. cpu_board_rev = get_cpu_board_revision();
  275. lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
  276. if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
  277. lsdmr_common |= LSDMR_BSMA1617;
  278. } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
  279. lsdmr_common |= LSDMR_BSMA1516;
  280. } else {
  281. /*
  282. * Assume something unable to identify itself is
  283. * really old, and likely has lines 16/17 mapped.
  284. */
  285. lsdmr_common |= LSDMR_BSMA1617;
  286. }
  287. /*
  288. * Issue PRECHARGE ALL command.
  289. */
  290. lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
  291. asm("sync;msync");
  292. *sdram_addr = 0xff;
  293. ppcDcbf((unsigned long) sdram_addr);
  294. udelay(100);
  295. /*
  296. * Issue 8 AUTO REFRESH commands.
  297. */
  298. for (idx = 0; idx < 8; idx++) {
  299. lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
  300. asm("sync;msync");
  301. *sdram_addr = 0xff;
  302. ppcDcbf((unsigned long) sdram_addr);
  303. udelay(100);
  304. }
  305. /*
  306. * Issue 8 MODE-set command.
  307. */
  308. lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
  309. asm("sync;msync");
  310. *sdram_addr = 0xff;
  311. ppcDcbf((unsigned long) sdram_addr);
  312. udelay(100);
  313. /*
  314. * Issue NORMAL OP command.
  315. */
  316. lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
  317. asm("sync;msync");
  318. *sdram_addr = 0xff;
  319. ppcDcbf((unsigned long) sdram_addr);
  320. udelay(200); /* Overkill. Must wait > 200 bus cycles */
  321. #endif /* enable SDRAM init */
  322. }
  323. #if defined(CONFIG_PCI)
  324. /* For some reason the Tundra PCI bridge shows up on itself as a
  325. * different device. Work around that by refusing to configure it.
  326. */
  327. void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
  328. static struct pci_config_table pci_mpc85xxcds_config_table[] = {
  329. {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
  330. {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
  331. {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
  332. mpc85xx_config_via_usbide, {0,0,0}},
  333. {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
  334. mpc85xx_config_via_usb, {0,0,0}},
  335. {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
  336. mpc85xx_config_via_usb2, {0,0,0}},
  337. {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
  338. mpc85xx_config_via_power, {0,0,0}},
  339. {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
  340. mpc85xx_config_via_ac97, {0,0,0}},
  341. {},
  342. };
  343. static struct pci_controller hose[] = {
  344. { config_table: pci_mpc85xxcds_config_table,},
  345. #ifdef CONFIG_MPC85XX_PCI2
  346. {},
  347. #endif
  348. };
  349. #endif /* CONFIG_PCI */
  350. void
  351. pci_init_board(void)
  352. {
  353. #ifdef CONFIG_PCI
  354. pci_mpc85xx_init(hose);
  355. #endif
  356. }
  357. #if defined(CONFIG_OF_BOARD_SETUP)
  358. void
  359. ft_pci_setup(void *blob, struct bd_info *bd)
  360. {
  361. int node, tmp[2];
  362. const char *path;
  363. node = fdt_path_offset(blob, "/aliases");
  364. tmp[0] = 0;
  365. if (node >= 0) {
  366. #ifdef CONFIG_PCI1
  367. path = fdt_getprop(blob, node, "pci0", NULL);
  368. if (path) {
  369. tmp[1] = hose[0].last_busno - hose[0].first_busno;
  370. do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
  371. }
  372. #endif
  373. #ifdef CONFIG_MPC85XX_PCI2
  374. path = fdt_getprop(blob, node, "pci1", NULL);
  375. if (path) {
  376. tmp[1] = hose[1].last_busno - hose[1].first_busno;
  377. do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
  378. }
  379. #endif
  380. }
  381. }
  382. #endif