mpc8349itx.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  4. */
  5. #include <common.h>
  6. #include <fdt_support.h>
  7. #include <init.h>
  8. #include <ioports.h>
  9. #include <log.h>
  10. #include <mpc83xx.h>
  11. #include <i2c.h>
  12. #include <miiphy.h>
  13. #include <vsc7385.h>
  14. #ifdef CONFIG_PCI
  15. #include <asm/mpc8349_pci.h>
  16. #include <pci.h>
  17. #endif
  18. #include <spd_sdram.h>
  19. #include <asm/bitops.h>
  20. #include <asm/mmu.h>
  21. #if defined(CONFIG_OF_LIBFDT)
  22. #include <linux/libfdt.h>
  23. #endif
  24. #include <linux/delay.h>
  25. #include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
  26. #include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #ifndef CONFIG_SPD_EEPROM
  29. /*************************************************************************
  30. * fixed sdram init -- doesn't use serial presence detect.
  31. ************************************************************************/
  32. int fixed_sdram(void)
  33. {
  34. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  35. /* The size of RAM, in bytes */
  36. u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
  37. u32 ddr_size_log2 = __ilog2(ddr_size);
  38. im->sysconf.ddrlaw[0].ar =
  39. LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  40. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  41. #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  42. #warning Chip select bounds is only configurable in 16MB increments
  43. #endif
  44. im->ddr.csbnds[0].csbnds =
  45. ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  46. (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
  47. CSBNDS_EA_SHIFT) & CSBNDS_EA);
  48. im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  49. /* Only one CS for DDR */
  50. im->ddr.cs_config[1] = 0;
  51. im->ddr.cs_config[2] = 0;
  52. im->ddr.cs_config[3] = 0;
  53. debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
  54. debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
  55. debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
  56. debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
  57. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  58. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
  59. im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
  60. im->ddr.sdram_mode =
  61. (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
  62. im->ddr.sdram_interval =
  63. (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
  64. SDRAM_INTERVAL_BSTOPRE_SHIFT);
  65. im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  66. udelay(200);
  67. im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  68. debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
  69. debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
  70. debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
  71. debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
  72. debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
  73. return CONFIG_SYS_DDR_SIZE;
  74. }
  75. #endif
  76. #ifdef CONFIG_PCI
  77. /*
  78. * Initialize PCI Devices, report devices found
  79. */
  80. #ifndef CONFIG_PCI_PNP
  81. static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
  82. {
  83. PCI_ANY_ID,
  84. PCI_ANY_ID,
  85. PCI_ANY_ID,
  86. PCI_ANY_ID,
  87. 0x0f,
  88. PCI_ANY_ID,
  89. pci_cfgfunc_config_device,
  90. {
  91. PCI_ENET0_IOADDR,
  92. PCI_ENET0_MEMADDR,
  93. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
  94. },
  95. {}
  96. }
  97. #endif
  98. volatile static struct pci_controller hose[] = {
  99. {
  100. #ifndef CONFIG_PCI_PNP
  101. config_table:pci_mpc83xxmitx_config_table,
  102. #endif
  103. },
  104. {
  105. #ifndef CONFIG_PCI_PNP
  106. config_table:pci_mpc83xxmitx_config_table,
  107. #endif
  108. }
  109. };
  110. #endif /* CONFIG_PCI */
  111. int dram_init(void)
  112. {
  113. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  114. u32 msize = 0;
  115. #ifdef CONFIG_DDR_ECC
  116. volatile ddr83xx_t *ddr = &im->ddr;
  117. #endif
  118. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  119. return -ENXIO;
  120. /* DDR SDRAM - Main SODIMM */
  121. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
  122. #ifdef CONFIG_SPD_EEPROM
  123. msize = spd_sdram();
  124. #else
  125. msize = fixed_sdram();
  126. #endif
  127. #ifdef CONFIG_DDR_ECC
  128. if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
  129. /* Unlike every other board, on the 83xx spd_sdram() returns
  130. megabytes instead of just bytes. That's why we need to
  131. multiple by 1MB when calling ddr_enable_ecc(). */
  132. ddr_enable_ecc(msize * 1048576);
  133. #endif
  134. /* return total bus RAM size(bytes) */
  135. gd->ram_size = msize * 1024 * 1024;
  136. return 0;
  137. }
  138. int checkboard(void)
  139. {
  140. #ifdef CONFIG_TARGET_MPC8349ITX
  141. puts("Board: Freescale MPC8349E-mITX\n");
  142. #else
  143. puts("Board: Freescale MPC8349E-mITX-GP\n");
  144. #endif
  145. return 0;
  146. }
  147. /*
  148. * Implement a work-around for a hardware problem with compact
  149. * flash.
  150. *
  151. * Program the UPM if compact flash is enabled.
  152. */
  153. int misc_init_f(void)
  154. {
  155. #ifdef CONFIG_VSC7385_ENET
  156. volatile u32 *vsc7385_cpuctrl;
  157. /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
  158. default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
  159. means it is 0 when the IRQ is not active. This makes the wire-AND
  160. logic always assert IRQ7 to CPU even if there is no request from the
  161. switch. Since the compact flash and the switch share the same IRQ,
  162. the Linux kernel will think that the compact flash is requesting irq
  163. and get stuck when it tries to clear the IRQ. Thus we need to set
  164. the L2_IRQ0 and L2_IRQ1 to active low.
  165. The following code sets the L1_IRQ and L2_IRQ polarity to active low.
  166. Without this code, compact flash will not work in Linux because
  167. unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
  168. don't enable compact flash for U-Boot.
  169. */
  170. vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
  171. *vsc7385_cpuctrl |= 0x0c;
  172. #endif
  173. #ifdef CONFIG_COMPACT_FLASH
  174. /* UPM Table Configuration Code */
  175. static uint UPMATable[] = {
  176. 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
  177. 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
  178. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  179. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  180. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
  181. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  182. 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
  183. 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
  184. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  185. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  186. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  187. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  188. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  189. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
  190. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
  191. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
  192. };
  193. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  194. set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
  195. set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
  196. /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
  197. GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
  198. */
  199. immap->im_lbc.mamr = 0x08404440;
  200. upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
  201. puts("UPMA: Configured for compact flash\n");
  202. #endif
  203. return 0;
  204. }
  205. /*
  206. * Miscellaneous late-boot configurations
  207. *
  208. * Make sure the EEPROM has the HRCW correctly programmed.
  209. * Make sure the RTC is correctly programmed.
  210. *
  211. * The MPC8349E-mITX can be configured to load the HRCW from
  212. * EEPROM instead of flash. This is controlled via jumpers
  213. * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
  214. * jumpered), but if they're set to 001 or 010, then the HRCW is
  215. * read from the "I2C EEPROM".
  216. *
  217. * This function makes sure that the I2C EEPROM is programmed
  218. * correctly.
  219. *
  220. * If a VSC7385 microcode image is present, then upload it.
  221. */
  222. int misc_init_r(void)
  223. {
  224. int rc = 0;
  225. #if defined(CONFIG_SYS_I2C)
  226. unsigned int orig_bus = i2c_get_bus_num();
  227. u8 i2c_data;
  228. #ifdef CONFIG_SYS_I2C_RTC_ADDR
  229. u8 ds1339_data[17];
  230. #endif
  231. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
  232. static u8 eeprom_data[] = /* HRCW data */
  233. {
  234. 0xAA, 0x55, 0xAA, /* Preamble */
  235. 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
  236. 0x02, 0x40, /* RCWL ADDR=0x0_0900 */
  237. (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
  238. (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
  239. (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
  240. CONFIG_SYS_HRCW_LOW & 0xFF,
  241. 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
  242. 0x02, 0x41, /* RCWH ADDR=0x0_0904 */
  243. (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
  244. (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
  245. (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
  246. CONFIG_SYS_HRCW_HIGH & 0xFF
  247. };
  248. u8 data[sizeof(eeprom_data)];
  249. #endif
  250. printf("Board revision: ");
  251. i2c_set_bus_num(1);
  252. if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
  253. printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
  254. else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
  255. printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
  256. else {
  257. printf("Unknown\n");
  258. rc = 1;
  259. }
  260. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
  261. i2c_set_bus_num(0);
  262. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
  263. if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
  264. if (i2c_write
  265. (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
  266. sizeof(eeprom_data)) != 0) {
  267. puts("Failure writing the HRCW to EEPROM via I2C.\n");
  268. rc = 1;
  269. }
  270. }
  271. } else {
  272. puts("Failure reading the HRCW from EEPROM via I2C.\n");
  273. rc = 1;
  274. }
  275. #endif
  276. #ifdef CONFIG_SYS_I2C_RTC_ADDR
  277. i2c_set_bus_num(1);
  278. if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
  279. == 0) {
  280. /* Work-around for MPC8349E-mITX bug #13601.
  281. If the RTC does not contain valid register values, the DS1339
  282. Linux driver will not work.
  283. */
  284. /* Make sure status register bits 6-2 are zero */
  285. ds1339_data[0x0f] &= ~0x7c;
  286. /* Check for a valid day register value */
  287. ds1339_data[0x03] &= ~0xf8;
  288. if (ds1339_data[0x03] == 0) {
  289. ds1339_data[0x03] = 1;
  290. }
  291. /* Check for a valid date register value */
  292. ds1339_data[0x04] &= ~0xc0;
  293. if ((ds1339_data[0x04] == 0) ||
  294. ((ds1339_data[0x04] & 0x0f) > 9) ||
  295. (ds1339_data[0x04] >= 0x32)) {
  296. ds1339_data[0x04] = 1;
  297. }
  298. /* Check for a valid month register value */
  299. ds1339_data[0x05] &= ~0x60;
  300. if ((ds1339_data[0x05] == 0) ||
  301. ((ds1339_data[0x05] & 0x0f) > 9) ||
  302. ((ds1339_data[0x05] >= 0x13)
  303. && (ds1339_data[0x05] <= 0x19))) {
  304. ds1339_data[0x05] = 1;
  305. }
  306. /* Enable Oscillator and rate select */
  307. ds1339_data[0x0e] = 0x1c;
  308. /* Work-around for MPC8349E-mITX bug #13330.
  309. Ensure that the RTC control register contains the value 0x1c.
  310. This affects SATA performance.
  311. */
  312. if (i2c_write
  313. (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
  314. sizeof(ds1339_data))) {
  315. puts("Failure writing to the RTC via I2C.\n");
  316. rc = 1;
  317. }
  318. } else {
  319. puts("Failure reading from the RTC via I2C.\n");
  320. rc = 1;
  321. }
  322. #endif
  323. i2c_set_bus_num(orig_bus);
  324. #endif
  325. #ifdef CONFIG_VSC7385_IMAGE
  326. if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
  327. CONFIG_VSC7385_IMAGE_SIZE)) {
  328. puts("Failure uploading VSC7385 microcode.\n");
  329. rc = 1;
  330. }
  331. #endif
  332. return rc;
  333. }
  334. #if defined(CONFIG_OF_BOARD_SETUP)
  335. int ft_board_setup(void *blob, struct bd_info *bd)
  336. {
  337. ft_cpu_setup(blob, bd);
  338. #ifdef CONFIG_PCI
  339. ft_pci_setup(blob, bd);
  340. #endif
  341. return 0;
  342. }
  343. #endif