m5249evb.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2004
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <init.h>
  9. #include <malloc.h>
  10. #include <asm/immap.h>
  11. #include <linux/delay.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. int checkboard (void) {
  14. ulong val;
  15. uchar val8;
  16. puts ("Board: ");
  17. puts("Freescale M5249EVB");
  18. val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
  19. printf(" (Switch=%1X)\n", val8);
  20. /*
  21. * Set LED on
  22. */
  23. val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
  24. mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
  25. return 0;
  26. };
  27. int dram_init(void)
  28. {
  29. unsigned long junk = 0xa5a59696;
  30. /*
  31. * Note:
  32. * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
  33. */
  34. #ifdef CONFIG_SYS_FAST_CLK
  35. /*
  36. * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
  37. * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
  38. */
  39. mbar_writeShort(MCFSIM_DCR, 0x8239);
  40. #elif CONFIG_SYS_PLL_BYPASS
  41. /*
  42. * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
  43. * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
  44. */
  45. mbar_writeShort(MCFSIM_DCR, 0x8202);
  46. #else
  47. /*
  48. * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
  49. * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
  50. */
  51. mbar_writeShort(MCFSIM_DCR, 0x8222);
  52. #endif
  53. /*
  54. * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
  55. * PM=1 (continuous page mode)
  56. */
  57. /* RE=0 (keep auto-refresh disabled while setting up registers) */
  58. mbar_writeLong(MCFSIM_DACR0, 0x00003324);
  59. /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
  60. mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
  61. /** Precharge sequence **/
  62. mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
  63. *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
  64. udelay(0x10); /* Allow several Precharge cycles */
  65. /** Refresh Sequence **/
  66. mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
  67. udelay(0x7d0); /* Allow gobs of refresh cycles */
  68. /** Mode Register initialization **/
  69. mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
  70. *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
  71. gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  72. return 0;
  73. };
  74. int testdram(void)
  75. {
  76. /* TODO: XXX XXX XXX */
  77. printf ("DRAM test not implemented!\n");
  78. return (0);
  79. }