ls2080aqds.c 7.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <init.h>
  8. #include <malloc.h>
  9. #include <errno.h>
  10. #include <netdev.h>
  11. #include <fsl_ifc.h>
  12. #include <fsl_ddr.h>
  13. #include <asm/io.h>
  14. #include <fdt_support.h>
  15. #include <linux/libfdt.h>
  16. #include <fsl-mc/fsl_mc.h>
  17. #include <env_internal.h>
  18. #include <i2c.h>
  19. #include <rtc.h>
  20. #include <asm/arch/soc.h>
  21. #include <hwconfig.h>
  22. #include <fsl_sec.h>
  23. #include <asm/arch/ppa.h>
  24. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  25. #include "../common/qixis.h"
  26. #include "ls2080aqds_qixis.h"
  27. #include "../common/vid.h"
  28. #define PIN_MUX_SEL_SDHC 0x00
  29. #define PIN_MUX_SEL_DSPI 0x0a
  30. #define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
  31. #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
  32. DECLARE_GLOBAL_DATA_PTR;
  33. enum {
  34. MUX_TYPE_SDHC,
  35. MUX_TYPE_DSPI,
  36. };
  37. unsigned long long get_qixis_addr(void)
  38. {
  39. unsigned long long addr;
  40. if (gd->flags & GD_FLG_RELOC)
  41. addr = QIXIS_BASE_PHYS;
  42. else
  43. addr = QIXIS_BASE_PHYS_EARLY;
  44. /*
  45. * IFC address under 256MB is mapped to 0x30000000, any address above
  46. * is mapped to 0x5_10000000 up to 4GB.
  47. */
  48. addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  49. return addr;
  50. }
  51. int checkboard(void)
  52. {
  53. char buf[64];
  54. u8 sw;
  55. static const char *const freq[] = {"100", "125", "156.25",
  56. "100 separate SSCG"};
  57. int clock;
  58. cpu_name(buf);
  59. printf("Board: %s-QDS, ", buf);
  60. sw = QIXIS_READ(arch);
  61. printf("Board Arch: V%d, ", sw >> 4);
  62. printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  63. memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
  64. sw = QIXIS_READ(brdcfg[0]);
  65. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  66. if (sw < 0x8)
  67. printf("vBank: %d\n", sw);
  68. else if (sw == 0x8)
  69. puts("PromJet\n");
  70. else if (sw == 0x9)
  71. puts("NAND\n");
  72. else if (sw == 0xf)
  73. puts("QSPI\n");
  74. else if (sw == 0x15)
  75. printf("IFCCard\n");
  76. else
  77. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  78. printf("FPGA: v%d (%s), build %d",
  79. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  80. (int)qixis_read_minor());
  81. /* the timestamp string contains "\n" at the end */
  82. printf(" on %s", qixis_read_time(buf));
  83. /*
  84. * Display the actual SERDES reference clocks as configured by the
  85. * dip switches on the board. Note that the SWx registers could
  86. * technically be set to force the reference clocks to match the
  87. * values that the SERDES expects (or vice versa). For now, however,
  88. * we just display both values and hope the user notices when they
  89. * don't match.
  90. */
  91. puts("SERDES1 Reference : ");
  92. sw = QIXIS_READ(brdcfg[2]);
  93. clock = (sw >> 6) & 3;
  94. printf("Clock1 = %sMHz ", freq[clock]);
  95. clock = (sw >> 4) & 3;
  96. printf("Clock2 = %sMHz", freq[clock]);
  97. puts("\nSERDES2 Reference : ");
  98. clock = (sw >> 2) & 3;
  99. printf("Clock1 = %sMHz ", freq[clock]);
  100. clock = (sw >> 0) & 3;
  101. printf("Clock2 = %sMHz\n", freq[clock]);
  102. return 0;
  103. }
  104. unsigned long get_board_sys_clk(void)
  105. {
  106. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  107. switch (sysclk_conf & 0x0F) {
  108. case QIXIS_SYSCLK_83:
  109. return 83333333;
  110. case QIXIS_SYSCLK_100:
  111. return 100000000;
  112. case QIXIS_SYSCLK_125:
  113. return 125000000;
  114. case QIXIS_SYSCLK_133:
  115. return 133333333;
  116. case QIXIS_SYSCLK_150:
  117. return 150000000;
  118. case QIXIS_SYSCLK_160:
  119. return 160000000;
  120. case QIXIS_SYSCLK_166:
  121. return 166666666;
  122. }
  123. return 66666666;
  124. }
  125. unsigned long get_board_ddr_clk(void)
  126. {
  127. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  128. switch ((ddrclk_conf & 0x30) >> 4) {
  129. case QIXIS_DDRCLK_100:
  130. return 100000000;
  131. case QIXIS_DDRCLK_125:
  132. return 125000000;
  133. case QIXIS_DDRCLK_133:
  134. return 133333333;
  135. }
  136. return 66666666;
  137. }
  138. int select_i2c_ch_pca9547(u8 ch)
  139. {
  140. int ret;
  141. #ifdef CONFIG_DM_I2C
  142. struct udevice *dev;
  143. ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  144. if (!ret)
  145. ret = dm_i2c_write(dev, 0, &ch, 1);
  146. #else
  147. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  148. #endif
  149. if (ret) {
  150. puts("PCA: failed to select proper channel\n");
  151. return ret;
  152. }
  153. return 0;
  154. }
  155. int config_board_mux(int ctrl_type)
  156. {
  157. u8 reg5;
  158. reg5 = QIXIS_READ(brdcfg[5]);
  159. switch (ctrl_type) {
  160. case MUX_TYPE_SDHC:
  161. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
  162. break;
  163. case MUX_TYPE_DSPI:
  164. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
  165. break;
  166. default:
  167. printf("Wrong mux interface type\n");
  168. return -1;
  169. }
  170. QIXIS_WRITE(brdcfg[5], reg5);
  171. return 0;
  172. }
  173. int board_init(void)
  174. {
  175. char *env_hwconfig;
  176. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  177. u32 val;
  178. init_final_memctl_regs();
  179. val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
  180. env_hwconfig = env_get("hwconfig");
  181. if (hwconfig_f("dspi", env_hwconfig) &&
  182. DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
  183. config_board_mux(MUX_TYPE_DSPI);
  184. else
  185. config_board_mux(MUX_TYPE_SDHC);
  186. #if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI)
  187. val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
  188. if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
  189. QIXIS_WRITE(brdcfg[9],
  190. (QIXIS_READ(brdcfg[9]) & 0xf8) |
  191. FSL_QIXIS_BRDCFG9_QSPI);
  192. #endif
  193. #ifdef CONFIG_ENV_IS_NOWHERE
  194. gd->env_addr = (ulong)&default_environment[0];
  195. #endif
  196. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  197. #ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
  198. #ifdef CONFIG_DM_I2C
  199. rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
  200. #else
  201. rtc_enable_32khz_output();
  202. #endif
  203. #endif
  204. #ifdef CONFIG_FSL_CAAM
  205. sec_init();
  206. #endif
  207. #ifdef CONFIG_FSL_LS_PPA
  208. ppa_init();
  209. #endif
  210. #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
  211. pci_init();
  212. #endif
  213. return 0;
  214. }
  215. int board_early_init_f(void)
  216. {
  217. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  218. i2c_early_init_f();
  219. #endif
  220. fsl_lsch3_early_init_f();
  221. #ifdef CONFIG_FSL_QSPI
  222. /* input clk: 1/2 platform clk, output: input/20 */
  223. out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
  224. #endif
  225. return 0;
  226. }
  227. int misc_init_r(void)
  228. {
  229. if (adjust_vdd(0))
  230. printf("Warning: Adjusting core voltage failed.\n");
  231. return 0;
  232. }
  233. void detail_board_ddr_info(void)
  234. {
  235. puts("\nDDR ");
  236. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  237. print_ddr_info(0);
  238. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  239. if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
  240. puts("\nDP-DDR ");
  241. print_size(gd->bd->bi_dram[2].size, "");
  242. print_ddr_info(CONFIG_DP_DDR_CTRL);
  243. }
  244. #endif
  245. }
  246. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  247. void fdt_fixup_board_enet(void *fdt)
  248. {
  249. int offset;
  250. offset = fdt_path_offset(fdt, "/soc/fsl-mc");
  251. if (offset < 0)
  252. offset = fdt_path_offset(fdt, "/fsl-mc");
  253. if (offset < 0) {
  254. printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
  255. __func__, offset);
  256. return;
  257. }
  258. if (get_mc_boot_status() == 0 &&
  259. (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
  260. fdt_status_okay(fdt, offset);
  261. else
  262. fdt_status_fail(fdt, offset);
  263. }
  264. void board_quiesce_devices(void)
  265. {
  266. fsl_mc_ldpaa_exit(gd->bd);
  267. }
  268. #endif
  269. #ifdef CONFIG_OF_BOARD_SETUP
  270. int ft_board_setup(void *blob, struct bd_info *bd)
  271. {
  272. u64 base[CONFIG_NR_DRAM_BANKS];
  273. u64 size[CONFIG_NR_DRAM_BANKS];
  274. ft_cpu_setup(blob, bd);
  275. /* fixup DT for the two GPP DDR banks */
  276. base[0] = gd->bd->bi_dram[0].start;
  277. size[0] = gd->bd->bi_dram[0].size;
  278. base[1] = gd->bd->bi_dram[1].start;
  279. size[1] = gd->bd->bi_dram[1].size;
  280. #ifdef CONFIG_RESV_RAM
  281. /* reduce size if reserved memory is within this bank */
  282. if (gd->arch.resv_ram >= base[0] &&
  283. gd->arch.resv_ram < base[0] + size[0])
  284. size[0] = gd->arch.resv_ram - base[0];
  285. else if (gd->arch.resv_ram >= base[1] &&
  286. gd->arch.resv_ram < base[1] + size[1])
  287. size[1] = gd->arch.resv_ram - base[1];
  288. #endif
  289. fdt_fixup_memory_banks(blob, base, size, 2);
  290. fdt_fsl_mc_fixup_iommu_map_entry(blob);
  291. fsl_fdt_fixup_dr_usb(blob, bd);
  292. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  293. fdt_fixup_board_enet(blob);
  294. #endif
  295. fdt_fixup_icid(blob);
  296. return 0;
  297. }
  298. #endif
  299. void qixis_dump_switch(void)
  300. {
  301. int i, nr_of_cfgsw;
  302. QIXIS_WRITE(cms[0], 0x00);
  303. nr_of_cfgsw = QIXIS_READ(cms[1]);
  304. puts("DIP switch settings dump:\n");
  305. for (i = 1; i <= nr_of_cfgsw; i++) {
  306. QIXIS_WRITE(cms[0], i);
  307. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  308. }
  309. }