ddr.h 2.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __DDR_H__
  6. #define __DDR_H__
  7. struct board_specific_parameters {
  8. u32 n_ranks;
  9. u32 datarate_mhz_high;
  10. u32 rank_gb;
  11. u32 clk_adjust;
  12. u32 wrlvl_start;
  13. u32 wrlvl_ctl_2;
  14. u32 wrlvl_ctl_3;
  15. };
  16. /*
  17. * These tables contain all valid speeds we want to override with board
  18. * specific parameters. datarate_mhz_high values need to be in ascending order
  19. * for each n_ranks group.
  20. */
  21. static const struct board_specific_parameters udimm0[] = {
  22. /*
  23. * memory controller 0
  24. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  25. * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  26. */
  27. {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
  28. {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
  29. {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
  30. {2, 2300, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
  31. {}
  32. };
  33. /* DP-DDR DIMM */
  34. static const struct board_specific_parameters udimm2[] = {
  35. /*
  36. * memory controller 2
  37. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  38. * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  39. */
  40. {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
  41. {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,},
  42. {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
  43. {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,},
  44. {}
  45. };
  46. static const struct board_specific_parameters rdimm0[] = {
  47. /*
  48. * memory controller 0
  49. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  50. * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  51. */
  52. {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
  53. {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
  54. {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
  55. {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
  56. {}
  57. };
  58. /* DP-DDR DIMM */
  59. static const struct board_specific_parameters rdimm2[] = {
  60. /*
  61. * memory controller 2
  62. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  63. * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  64. */
  65. {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
  66. {2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,},
  67. {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
  68. {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,},
  69. {}
  70. };
  71. static const struct board_specific_parameters *udimms[] = {
  72. udimm0,
  73. udimm0,
  74. udimm2,
  75. };
  76. static const struct board_specific_parameters *rdimms[] = {
  77. rdimm0,
  78. rdimm0,
  79. rdimm2,
  80. };
  81. #endif