eth.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. */
  6. #include <common.h>
  7. #include <log.h>
  8. #include <net.h>
  9. #include <asm/io.h>
  10. #include <netdev.h>
  11. #include <fdt_support.h>
  12. #include <fm_eth.h>
  13. #include <fsl_mdio.h>
  14. #include <fsl_dtsec.h>
  15. #include <linux/libfdt.h>
  16. #include <malloc.h>
  17. #include <asm/arch/fsl_serdes.h>
  18. #include "../common/qixis.h"
  19. #include "../common/fman.h"
  20. #include "ls1043aqds_qixis.h"
  21. #define EMI_NONE 0xFF
  22. #define EMI1_RGMII1 0
  23. #define EMI1_RGMII2 1
  24. #define EMI1_SLOT1 2
  25. #define EMI1_SLOT2 3
  26. #define EMI1_SLOT3 4
  27. #define EMI1_SLOT4 5
  28. #define EMI2 6
  29. static int mdio_mux[NUM_FM_PORTS];
  30. static const char * const mdio_names[] = {
  31. "LS1043AQDS_MDIO_RGMII1",
  32. "LS1043AQDS_MDIO_RGMII2",
  33. "LS1043AQDS_MDIO_SLOT1",
  34. "LS1043AQDS_MDIO_SLOT2",
  35. "LS1043AQDS_MDIO_SLOT3",
  36. "LS1043AQDS_MDIO_SLOT4",
  37. "NULL",
  38. };
  39. /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
  40. static u8 lane_to_slot[] = {1, 2, 3, 4};
  41. static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval)
  42. {
  43. return mdio_names[muxval];
  44. }
  45. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  46. {
  47. struct mii_dev *bus;
  48. const char *name;
  49. if (muxval > EMI2)
  50. return NULL;
  51. name = ls1043aqds_mdio_name_for_muxval(muxval);
  52. if (!name) {
  53. printf("No bus for muxval %x\n", muxval);
  54. return NULL;
  55. }
  56. bus = miiphy_get_dev_by_name(name);
  57. if (!bus) {
  58. printf("No bus by name %s\n", name);
  59. return NULL;
  60. }
  61. return bus;
  62. }
  63. struct ls1043aqds_mdio {
  64. u8 muxval;
  65. struct mii_dev *realbus;
  66. };
  67. static void ls1043aqds_mux_mdio(u8 muxval)
  68. {
  69. u8 brdcfg4;
  70. if (muxval < 7) {
  71. brdcfg4 = QIXIS_READ(brdcfg[4]);
  72. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  73. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  74. QIXIS_WRITE(brdcfg[4], brdcfg4);
  75. }
  76. }
  77. static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
  78. int regnum)
  79. {
  80. struct ls1043aqds_mdio *priv = bus->priv;
  81. ls1043aqds_mux_mdio(priv->muxval);
  82. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  83. }
  84. static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
  85. int regnum, u16 value)
  86. {
  87. struct ls1043aqds_mdio *priv = bus->priv;
  88. ls1043aqds_mux_mdio(priv->muxval);
  89. return priv->realbus->write(priv->realbus, addr, devad,
  90. regnum, value);
  91. }
  92. static int ls1043aqds_mdio_reset(struct mii_dev *bus)
  93. {
  94. struct ls1043aqds_mdio *priv = bus->priv;
  95. return priv->realbus->reset(priv->realbus);
  96. }
  97. static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
  98. {
  99. struct ls1043aqds_mdio *pmdio;
  100. struct mii_dev *bus = mdio_alloc();
  101. if (!bus) {
  102. printf("Failed to allocate ls1043aqds MDIO bus\n");
  103. return -1;
  104. }
  105. pmdio = malloc(sizeof(*pmdio));
  106. if (!pmdio) {
  107. printf("Failed to allocate ls1043aqds private data\n");
  108. free(bus);
  109. return -1;
  110. }
  111. bus->read = ls1043aqds_mdio_read;
  112. bus->write = ls1043aqds_mdio_write;
  113. bus->reset = ls1043aqds_mdio_reset;
  114. strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
  115. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  116. if (!pmdio->realbus) {
  117. printf("No bus with name %s\n", realbusname);
  118. free(bus);
  119. free(pmdio);
  120. return -1;
  121. }
  122. pmdio->muxval = muxval;
  123. bus->priv = pmdio;
  124. return mdio_register(bus);
  125. }
  126. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  127. enum fm_port port, int offset)
  128. {
  129. struct fixed_link f_link;
  130. if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
  131. if (port == FM1_DTSEC9) {
  132. fdt_set_phy_handle(fdt, compat, addr,
  133. "sgmii-riser-s1-p1");
  134. } else if (port == FM1_DTSEC2) {
  135. fdt_set_phy_handle(fdt, compat, addr,
  136. "sgmii-riser-s2-p1");
  137. } else if (port == FM1_DTSEC5) {
  138. fdt_set_phy_handle(fdt, compat, addr,
  139. "sgmii-riser-s3-p1");
  140. } else if (port == FM1_DTSEC6) {
  141. fdt_set_phy_handle(fdt, compat, addr,
  142. "sgmii-riser-s4-p1");
  143. }
  144. } else if (fm_info_get_enet_if(port) ==
  145. PHY_INTERFACE_MODE_SGMII_2500) {
  146. /* 2.5G SGMII interface */
  147. f_link.phy_id = cpu_to_fdt32(port);
  148. f_link.duplex = cpu_to_fdt32(1);
  149. f_link.link_speed = cpu_to_fdt32(1000);
  150. f_link.pause = 0;
  151. f_link.asym_pause = 0;
  152. /* no PHY for 2.5G SGMII */
  153. fdt_delprop(fdt, offset, "phy-handle");
  154. fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
  155. fdt_setprop_string(fdt, offset, "phy-connection-type",
  156. "sgmii-2500");
  157. } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
  158. switch (mdio_mux[port]) {
  159. case EMI1_SLOT1:
  160. switch (port) {
  161. case FM1_DTSEC1:
  162. fdt_set_phy_handle(fdt, compat, addr,
  163. "qsgmii-s1-p1");
  164. break;
  165. case FM1_DTSEC2:
  166. fdt_set_phy_handle(fdt, compat, addr,
  167. "qsgmii-s1-p2");
  168. break;
  169. case FM1_DTSEC5:
  170. fdt_set_phy_handle(fdt, compat, addr,
  171. "qsgmii-s1-p3");
  172. break;
  173. case FM1_DTSEC6:
  174. fdt_set_phy_handle(fdt, compat, addr,
  175. "qsgmii-s1-p4");
  176. break;
  177. default:
  178. break;
  179. }
  180. break;
  181. case EMI1_SLOT2:
  182. switch (port) {
  183. case FM1_DTSEC1:
  184. fdt_set_phy_handle(fdt, compat, addr,
  185. "qsgmii-s2-p1");
  186. break;
  187. case FM1_DTSEC2:
  188. fdt_set_phy_handle(fdt, compat, addr,
  189. "qsgmii-s2-p2");
  190. break;
  191. case FM1_DTSEC5:
  192. fdt_set_phy_handle(fdt, compat, addr,
  193. "qsgmii-s2-p3");
  194. break;
  195. case FM1_DTSEC6:
  196. fdt_set_phy_handle(fdt, compat, addr,
  197. "qsgmii-s2-p4");
  198. break;
  199. default:
  200. break;
  201. }
  202. break;
  203. default:
  204. break;
  205. }
  206. fdt_delprop(fdt, offset, "phy-connection-type");
  207. fdt_setprop_string(fdt, offset, "phy-connection-type",
  208. "qsgmii");
  209. } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
  210. port == FM1_10GEC1) {
  211. /* XFI interface */
  212. f_link.phy_id = cpu_to_fdt32(port);
  213. f_link.duplex = cpu_to_fdt32(1);
  214. f_link.link_speed = cpu_to_fdt32(10000);
  215. f_link.pause = 0;
  216. f_link.asym_pause = 0;
  217. /* no PHY for XFI */
  218. fdt_delprop(fdt, offset, "phy-handle");
  219. fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
  220. fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
  221. }
  222. }
  223. void fdt_fixup_board_enet(void *fdt)
  224. {
  225. int i;
  226. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  227. u32 srds_s1;
  228. srds_s1 = in_be32(&gur->rcwsr[4]) &
  229. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  230. srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  231. for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
  232. switch (fm_info_get_enet_if(i)) {
  233. case PHY_INTERFACE_MODE_SGMII:
  234. case PHY_INTERFACE_MODE_QSGMII:
  235. switch (mdio_mux[i]) {
  236. case EMI1_SLOT1:
  237. fdt_status_okay_by_alias(fdt, "emi1-slot1");
  238. break;
  239. case EMI1_SLOT2:
  240. fdt_status_okay_by_alias(fdt, "emi1-slot2");
  241. break;
  242. case EMI1_SLOT3:
  243. fdt_status_okay_by_alias(fdt, "emi1-slot3");
  244. break;
  245. case EMI1_SLOT4:
  246. fdt_status_okay_by_alias(fdt, "emi1-slot4");
  247. break;
  248. default:
  249. break;
  250. }
  251. break;
  252. case PHY_INTERFACE_MODE_XGMII:
  253. break;
  254. default:
  255. break;
  256. }
  257. }
  258. }
  259. int board_eth_init(struct bd_info *bis)
  260. {
  261. #ifdef CONFIG_FMAN_ENET
  262. int i, idx, lane, slot, interface;
  263. struct memac_mdio_info dtsec_mdio_info;
  264. struct memac_mdio_info tgec_mdio_info;
  265. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  266. u32 srds_s1;
  267. srds_s1 = in_be32(&gur->rcwsr[4]) &
  268. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  269. srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  270. /* Initialize the mdio_mux array so we can recognize empty elements */
  271. for (i = 0; i < NUM_FM_PORTS; i++)
  272. mdio_mux[i] = EMI_NONE;
  273. dtsec_mdio_info.regs =
  274. (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  275. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  276. /* Register the 1G MDIO bus */
  277. fm_memac_mdio_init(bis, &dtsec_mdio_info);
  278. tgec_mdio_info.regs =
  279. (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  280. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  281. /* Register the 10G MDIO bus */
  282. fm_memac_mdio_init(bis, &tgec_mdio_info);
  283. /* Register the muxing front-ends to the MDIO buses */
  284. ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
  285. ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
  286. ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
  287. ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
  288. ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
  289. ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
  290. ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
  291. /* Set the two on-board RGMII PHY address */
  292. fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
  293. fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
  294. switch (srds_s1) {
  295. case 0x2555:
  296. /* 2.5G SGMII on lane A, MAC 9 */
  297. fm_info_set_phy_address(FM1_DTSEC9, 9);
  298. break;
  299. case 0x4555:
  300. case 0x4558:
  301. /* QSGMII on lane A, MAC 1/2/5/6 */
  302. fm_info_set_phy_address(FM1_DTSEC1,
  303. QSGMII_CARD_PORT1_PHY_ADDR_S1);
  304. fm_info_set_phy_address(FM1_DTSEC2,
  305. QSGMII_CARD_PORT2_PHY_ADDR_S1);
  306. fm_info_set_phy_address(FM1_DTSEC5,
  307. QSGMII_CARD_PORT3_PHY_ADDR_S1);
  308. fm_info_set_phy_address(FM1_DTSEC6,
  309. QSGMII_CARD_PORT4_PHY_ADDR_S1);
  310. break;
  311. case 0x1355:
  312. /* SGMII on lane B, MAC 2*/
  313. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  314. break;
  315. case 0x2355:
  316. /* 2.5G SGMII on lane A, MAC 9 */
  317. fm_info_set_phy_address(FM1_DTSEC9, 9);
  318. /* SGMII on lane B, MAC 2*/
  319. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  320. break;
  321. case 0x3335:
  322. /* SGMII on lane C, MAC 5 */
  323. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
  324. case 0x3355:
  325. case 0x3358:
  326. /* SGMII on lane B, MAC 2 */
  327. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
  328. case 0x3555:
  329. case 0x3558:
  330. /* SGMII on lane A, MAC 9 */
  331. fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
  332. break;
  333. case 0x1455:
  334. /* QSGMII on lane B, MAC 1/2/5/6 */
  335. fm_info_set_phy_address(FM1_DTSEC1,
  336. QSGMII_CARD_PORT1_PHY_ADDR_S2);
  337. fm_info_set_phy_address(FM1_DTSEC2,
  338. QSGMII_CARD_PORT2_PHY_ADDR_S2);
  339. fm_info_set_phy_address(FM1_DTSEC5,
  340. QSGMII_CARD_PORT3_PHY_ADDR_S2);
  341. fm_info_set_phy_address(FM1_DTSEC6,
  342. QSGMII_CARD_PORT4_PHY_ADDR_S2);
  343. break;
  344. case 0x2455:
  345. /* 2.5G SGMII on lane A, MAC 9 */
  346. fm_info_set_phy_address(FM1_DTSEC9, 9);
  347. /* QSGMII on lane B, MAC 1/2/5/6 */
  348. fm_info_set_phy_address(FM1_DTSEC1,
  349. QSGMII_CARD_PORT1_PHY_ADDR_S2);
  350. fm_info_set_phy_address(FM1_DTSEC2,
  351. QSGMII_CARD_PORT2_PHY_ADDR_S2);
  352. fm_info_set_phy_address(FM1_DTSEC5,
  353. QSGMII_CARD_PORT3_PHY_ADDR_S2);
  354. fm_info_set_phy_address(FM1_DTSEC6,
  355. QSGMII_CARD_PORT4_PHY_ADDR_S2);
  356. break;
  357. case 0x2255:
  358. /* 2.5G SGMII on lane A, MAC 9 */
  359. fm_info_set_phy_address(FM1_DTSEC9, 9);
  360. /* 2.5G SGMII on lane B, MAC 2 */
  361. fm_info_set_phy_address(FM1_DTSEC2, 2);
  362. break;
  363. case 0x3333:
  364. /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */
  365. fm_info_set_phy_address(FM1_DTSEC9,
  366. SGMII_CARD_PORT1_PHY_ADDR);
  367. fm_info_set_phy_address(FM1_DTSEC2,
  368. SGMII_CARD_PORT1_PHY_ADDR);
  369. fm_info_set_phy_address(FM1_DTSEC5,
  370. SGMII_CARD_PORT1_PHY_ADDR);
  371. fm_info_set_phy_address(FM1_DTSEC6,
  372. SGMII_CARD_PORT1_PHY_ADDR);
  373. break;
  374. default:
  375. printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n",
  376. srds_s1);
  377. break;
  378. }
  379. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  380. idx = i - FM1_DTSEC1;
  381. interface = fm_info_get_enet_if(i);
  382. switch (interface) {
  383. case PHY_INTERFACE_MODE_SGMII:
  384. case PHY_INTERFACE_MODE_SGMII_2500:
  385. case PHY_INTERFACE_MODE_QSGMII:
  386. if (interface == PHY_INTERFACE_MODE_SGMII) {
  387. lane = serdes_get_first_lane(FSL_SRDS_1,
  388. SGMII_FM1_DTSEC1 + idx);
  389. } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
  390. lane = serdes_get_first_lane(FSL_SRDS_1,
  391. SGMII_2500_FM1_DTSEC1 + idx);
  392. } else {
  393. lane = serdes_get_first_lane(FSL_SRDS_1,
  394. QSGMII_FM1_A);
  395. }
  396. if (lane < 0)
  397. break;
  398. slot = lane_to_slot[lane];
  399. debug("FM1@DTSEC%u expects SGMII in slot %u\n",
  400. idx + 1, slot);
  401. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  402. fm_disable_port(i);
  403. switch (slot) {
  404. case 1:
  405. mdio_mux[i] = EMI1_SLOT1;
  406. fm_info_set_mdio(i, mii_dev_for_muxval(
  407. mdio_mux[i]));
  408. break;
  409. case 2:
  410. mdio_mux[i] = EMI1_SLOT2;
  411. fm_info_set_mdio(i, mii_dev_for_muxval(
  412. mdio_mux[i]));
  413. break;
  414. case 3:
  415. mdio_mux[i] = EMI1_SLOT3;
  416. fm_info_set_mdio(i, mii_dev_for_muxval(
  417. mdio_mux[i]));
  418. break;
  419. case 4:
  420. mdio_mux[i] = EMI1_SLOT4;
  421. fm_info_set_mdio(i, mii_dev_for_muxval(
  422. mdio_mux[i]));
  423. break;
  424. default:
  425. break;
  426. }
  427. break;
  428. case PHY_INTERFACE_MODE_RGMII:
  429. case PHY_INTERFACE_MODE_RGMII_TXID:
  430. case PHY_INTERFACE_MODE_RGMII_RXID:
  431. case PHY_INTERFACE_MODE_RGMII_ID:
  432. if (i == FM1_DTSEC3)
  433. mdio_mux[i] = EMI1_RGMII1;
  434. else if (i == FM1_DTSEC4)
  435. mdio_mux[i] = EMI1_RGMII2;
  436. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  437. break;
  438. default:
  439. break;
  440. }
  441. }
  442. cpu_eth_init(bis);
  443. #endif /* CONFIG_FMAN_ENET */
  444. return pci_eth_init(bis);
  445. }