ddr.h 1.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __DDR_H__
  6. #define __DDR_H__
  7. extern void erratum_a008850_post(void);
  8. struct board_specific_parameters {
  9. u32 n_ranks;
  10. u32 datarate_mhz_high;
  11. u32 rank_gb;
  12. u32 clk_adjust;
  13. u32 wrlvl_start;
  14. u32 wrlvl_ctl_2;
  15. u32 wrlvl_ctl_3;
  16. u32 cpo_override;
  17. u32 write_data_delay;
  18. u32 force_2t;
  19. };
  20. /*
  21. * These tables contain all valid speeds we want to override with board
  22. * specific parameters. datarate_mhz_high values need to be in ascending order
  23. * for each n_ranks group.
  24. */
  25. static const struct board_specific_parameters udimm0[] = {
  26. /*
  27. * memory controller 0
  28. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
  29. * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
  30. */
  31. #ifdef CONFIG_SYS_FSL_DDR4
  32. {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
  33. {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
  34. {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E0A,},
  35. {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
  36. {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,},
  37. #elif defined(CONFIG_SYS_FSL_DDR3)
  38. {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
  39. {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
  40. {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
  41. {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
  42. {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
  43. {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
  44. {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
  45. {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
  46. {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
  47. #else
  48. #error DDR type not defined
  49. #endif
  50. {}
  51. };
  52. static const struct board_specific_parameters *udimms[] = {
  53. udimm0,
  54. };
  55. #endif