ddr.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fsl_ddr_sdram.h>
  7. #include <fsl_ddr_dimm_params.h>
  8. #ifdef CONFIG_FSL_DEEP_SLEEP
  9. #include <fsl_sleep.h>
  10. #endif
  11. #include <log.h>
  12. #include <asm/arch/clock.h>
  13. #include "ddr.h"
  14. DECLARE_GLOBAL_DATA_PTR;
  15. void fsl_ddr_board_options(memctl_options_t *popts,
  16. dimm_params_t *pdimm,
  17. unsigned int ctrl_num)
  18. {
  19. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  20. ulong ddr_freq;
  21. if (ctrl_num > 3) {
  22. printf("Not supported controller number %d\n", ctrl_num);
  23. return;
  24. }
  25. if (!pdimm->n_ranks)
  26. return;
  27. pbsp = udimms[0];
  28. /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  29. * freqency and n_banks specified in board_specific_parameters table.
  30. */
  31. ddr_freq = get_ddr_freq(0) / 1000000;
  32. while (pbsp->datarate_mhz_high) {
  33. if (pbsp->n_ranks == pdimm->n_ranks) {
  34. if (ddr_freq <= pbsp->datarate_mhz_high) {
  35. popts->clk_adjust = pbsp->clk_adjust;
  36. popts->wrlvl_start = pbsp->wrlvl_start;
  37. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  38. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  39. popts->cpo_override = pbsp->cpo_override;
  40. popts->write_data_delay =
  41. pbsp->write_data_delay;
  42. goto found;
  43. }
  44. pbsp_highest = pbsp;
  45. }
  46. pbsp++;
  47. }
  48. if (pbsp_highest) {
  49. printf("Error: board specific timing not found for %lu MT/s\n",
  50. ddr_freq);
  51. printf("Trying to use the highest speed (%u) parameters\n",
  52. pbsp_highest->datarate_mhz_high);
  53. popts->clk_adjust = pbsp_highest->clk_adjust;
  54. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  55. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  56. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  57. } else {
  58. panic("DIMM is not supported by this board");
  59. }
  60. found:
  61. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
  62. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
  63. /* force DDR bus width to 32 bits */
  64. popts->data_bus_width = 1;
  65. popts->otf_burst_chop_en = 0;
  66. popts->burst_length = DDR_BL8;
  67. popts->bstopre = 0; /* enable auto precharge */
  68. /*
  69. * Factors to consider for half-strength driver enable:
  70. * - number of DIMMs installed
  71. */
  72. popts->half_strength_driver_enable = 1;
  73. /*
  74. * Write leveling override
  75. */
  76. popts->wrlvl_override = 1;
  77. popts->wrlvl_sample = 0xf;
  78. /*
  79. * Rtt and Rtt_WR override
  80. */
  81. popts->rtt_override = 0;
  82. /* Enable ZQ calibration */
  83. popts->zq_en = 1;
  84. #ifdef CONFIG_SYS_FSL_DDR4
  85. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  86. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  87. DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
  88. /* optimize cpo for erratum A-009942 */
  89. popts->cpo_sample = 0x59;
  90. #else
  91. popts->cswl_override = DDR_CSWL_CS0;
  92. /* DHC_EN =1, ODT = 75 Ohm */
  93. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  94. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  95. #endif
  96. }
  97. #ifdef CONFIG_TFABOOT
  98. int fsl_initdram(void)
  99. {
  100. gd->ram_size = tfa_get_dram_size();
  101. if (!gd->ram_size)
  102. gd->ram_size = fsl_ddr_sdram_size();
  103. return 0;
  104. }
  105. #else
  106. int fsl_initdram(void)
  107. {
  108. phys_size_t dram_size;
  109. #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
  110. gd->ram_size = fsl_ddr_sdram_size();
  111. return 0;
  112. #else
  113. puts("Initializing DDR....using SPD\n");
  114. dram_size = fsl_ddr_sdram();
  115. #endif
  116. erratum_a008850_post();
  117. #ifdef CONFIG_FSL_DEEP_SLEEP
  118. fsl_dp_ddr_restore();
  119. #endif
  120. gd->ram_size = dram_size;
  121. return 0;
  122. }
  123. #endif