spl.c 2.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120
  1. /*
  2. * Copyright 2018-2019 NXP
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <cpu_func.h>
  9. #include <hang.h>
  10. #include <image.h>
  11. #include <init.h>
  12. #include <log.h>
  13. #include <spl.h>
  14. #include <asm/io.h>
  15. #include <asm/mach-imx/iomux-v3.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/imx8mn_pins.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/mach-imx/boot_mode.h>
  20. #include <asm/arch/ddr.h>
  21. #include <dm/uclass.h>
  22. #include <dm/device.h>
  23. #include <dm/uclass-internal.h>
  24. #include <dm/device-internal.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. int spl_board_boot_device(enum boot_device boot_dev_spl)
  27. {
  28. return BOOT_DEVICE_BOOTROM;
  29. }
  30. void spl_dram_init(void)
  31. {
  32. ddr_init(&dram_timing);
  33. }
  34. void spl_board_init(void)
  35. {
  36. struct udevice *dev;
  37. int ret;
  38. puts("Normal Boot\n");
  39. ret = uclass_get_device_by_name(UCLASS_CLK,
  40. "clock-controller@30380000",
  41. &dev);
  42. if (ret < 0)
  43. printf("Failed to find clock node. Check device tree\n");
  44. }
  45. #ifdef CONFIG_SPL_LOAD_FIT
  46. int board_fit_config_name_match(const char *name)
  47. {
  48. /* Just empty function now - can't decide what to choose */
  49. debug("%s: %s\n", __func__, name);
  50. return 0;
  51. }
  52. #endif
  53. #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  54. #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  55. static iomux_v3_cfg_t const uart_pads[] = {
  56. IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  57. IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  58. };
  59. static iomux_v3_cfg_t const wdog_pads[] = {
  60. IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  61. };
  62. int board_early_init_f(void)
  63. {
  64. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  65. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  66. set_wdog_reset(wdog);
  67. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  68. init_uart_clk(1);
  69. return 0;
  70. }
  71. void board_init_f(ulong dummy)
  72. {
  73. int ret;
  74. arch_cpu_init();
  75. init_uart_clk(1);
  76. board_early_init_f();
  77. timer_init();
  78. preloader_console_init();
  79. /* Clear the BSS. */
  80. memset(__bss_start, 0, __bss_end - __bss_start);
  81. ret = spl_init();
  82. if (ret) {
  83. debug("spl_init() failed: %d\n", ret);
  84. hang();
  85. }
  86. enable_tzc380();
  87. /* DDR initialization */
  88. spl_dram_init();
  89. board_init_r(NULL, 0);
  90. }