spl.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <cpu_func.h>
  8. #include <hang.h>
  9. #include <image.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <spl.h>
  13. #include <asm/io.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/imx8mm_pins.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/mach-imx/boot_mode.h>
  19. #include <asm/arch/ddr.h>
  20. #include <dm/uclass.h>
  21. #include <dm/device.h>
  22. #include <dm/uclass-internal.h>
  23. #include <dm/device-internal.h>
  24. #include <power/pmic.h>
  25. #include <power/bd71837.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. int spl_board_boot_device(enum boot_device boot_dev_spl)
  28. {
  29. switch (boot_dev_spl) {
  30. case SD2_BOOT:
  31. case MMC2_BOOT:
  32. return BOOT_DEVICE_MMC1;
  33. case SD3_BOOT:
  34. case MMC3_BOOT:
  35. return BOOT_DEVICE_MMC2;
  36. default:
  37. return BOOT_DEVICE_NONE;
  38. }
  39. }
  40. static void spl_dram_init(void)
  41. {
  42. ddr_init(&dram_timing);
  43. }
  44. void spl_board_init(void)
  45. {
  46. puts("Normal Boot\n");
  47. }
  48. #ifdef CONFIG_SPL_LOAD_FIT
  49. int board_fit_config_name_match(const char *name)
  50. {
  51. /* Just empty function now - can't decide what to choose */
  52. debug("%s: %s\n", __func__, name);
  53. return 0;
  54. }
  55. #endif
  56. #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  57. #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  58. static iomux_v3_cfg_t const uart_pads[] = {
  59. IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  60. IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  61. };
  62. static iomux_v3_cfg_t const wdog_pads[] = {
  63. IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  64. };
  65. int board_early_init_f(void)
  66. {
  67. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  68. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  69. set_wdog_reset(wdog);
  70. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  71. return 0;
  72. }
  73. static int power_init_board(void)
  74. {
  75. struct udevice *dev;
  76. int ret;
  77. ret = pmic_get("pmic@4b", &dev);
  78. if (ret == -ENODEV) {
  79. puts("No pmic\n");
  80. return 0;
  81. }
  82. if (ret != 0)
  83. return ret;
  84. /* decrease RESET key long push time from the default 10s to 10ms */
  85. pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
  86. /* unlock the PMIC regs */
  87. pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
  88. /* increase VDD_SOC to typical value 0.85v before first DRAM access */
  89. pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
  90. /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
  91. pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
  92. #ifndef CONFIG_IMX8M_LPDDR4
  93. /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
  94. pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
  95. #endif
  96. /* lock the PMIC regs */
  97. pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
  98. return 0;
  99. }
  100. void board_init_f(ulong dummy)
  101. {
  102. struct udevice *dev;
  103. int ret;
  104. arch_cpu_init();
  105. init_uart_clk(1);
  106. board_early_init_f();
  107. timer_init();
  108. preloader_console_init();
  109. /* Clear the BSS. */
  110. memset(__bss_start, 0, __bss_end - __bss_start);
  111. ret = spl_early_init();
  112. if (ret) {
  113. debug("spl_early_init() failed: %d\n", ret);
  114. hang();
  115. }
  116. ret = uclass_get_device_by_name(UCLASS_CLK,
  117. "clock-controller@30380000",
  118. &dev);
  119. if (ret < 0) {
  120. printf("Failed to find clock node. Check device tree\n");
  121. hang();
  122. }
  123. enable_tzc380();
  124. power_init_board();
  125. /* DDR initialization */
  126. spl_dram_init();
  127. board_init_r(NULL, 0);
  128. }