p4080ds_ddr.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fsl_ddr_sdram.h>
  7. #define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
  8. #define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
  9. #define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
  10. #define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
  11. #define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
  12. #define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
  13. #define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
  14. #define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
  15. #define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000
  16. #define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104
  17. #define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944
  18. #define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF
  19. #define CONFIG_SYS_DDR_MODE_1_1000 0x00441830
  20. #define CONFIG_SYS_DDR_MODE_2_1000 0x00080000
  21. #define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100
  22. #define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000
  23. #define CONFIG_SYS_DDR_TIMING_3_900 0x00020000
  24. #define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104
  25. #define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844
  26. #define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce
  27. #define CONFIG_SYS_DDR_MODE_1_900 0x00441620
  28. #define CONFIG_SYS_DDR_MODE_2_900 0x00080000
  29. #define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100
  30. #define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000
  31. #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
  32. #define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104
  33. #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744
  34. #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc
  35. #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
  36. #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
  37. #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
  38. #define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
  39. #define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF
  40. #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
  41. #define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF
  42. #define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF
  43. #define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF
  44. #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
  45. #define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF
  46. #define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF
  47. #define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202
  48. #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  49. #define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
  50. #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
  51. #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
  52. #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202
  53. #define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202
  54. #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
  55. #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
  56. #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  57. #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  58. #define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
  59. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  60. #define CONFIG_SYS_DDR_TIMING_4 0x00000001
  61. #define CONFIG_SYS_DDR_TIMING_5 0x02401400
  62. #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  63. #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
  64. #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607
  65. #define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000
  66. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
  67. #define CONFIG_SYS_DDR_RCW_1 0x00000000
  68. #define CONFIG_SYS_DDR_RCW_2 0x00000000
  69. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  70. fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
  71. .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  72. .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
  73. .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
  74. .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
  75. .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  76. .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  77. .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
  78. .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
  79. .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
  80. .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
  81. .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
  82. .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
  83. .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
  84. .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
  85. .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
  86. .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
  87. .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
  88. .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  89. .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
  90. .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  91. .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
  92. .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  93. .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  94. .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  95. .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  96. .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
  97. .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
  98. .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  99. .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  100. };
  101. fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = {
  102. .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
  103. .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
  104. .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
  105. .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
  106. .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
  107. .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  108. .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
  109. .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
  110. .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
  111. .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
  112. .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
  113. .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
  114. .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
  115. .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
  116. .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
  117. .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
  118. .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
  119. .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  120. .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
  121. .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  122. .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
  123. .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  124. .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  125. .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  126. .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  127. .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
  128. .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
  129. .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  130. .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  131. };
  132. fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
  133. .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  134. .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
  135. .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
  136. .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
  137. .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  138. .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  139. .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
  140. .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
  141. .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
  142. .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
  143. .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
  144. .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
  145. .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
  146. .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
  147. .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
  148. .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
  149. .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
  150. .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  151. .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
  152. .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  153. .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
  154. .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  155. .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  156. .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  157. .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  158. .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
  159. .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
  160. .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  161. .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  162. };
  163. fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = {
  164. .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
  165. .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
  166. .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
  167. .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
  168. .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
  169. .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  170. .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
  171. .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
  172. .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
  173. .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
  174. .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
  175. .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
  176. .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
  177. .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
  178. .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
  179. .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
  180. .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
  181. .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  182. .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
  183. .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  184. .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
  185. .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  186. .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  187. .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  188. .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  189. .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
  190. .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
  191. .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  192. .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  193. };
  194. fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
  195. .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  196. .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
  197. .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
  198. .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
  199. .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  200. .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  201. .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
  202. .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
  203. .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
  204. .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
  205. .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
  206. .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
  207. .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
  208. .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
  209. .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
  210. .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
  211. .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
  212. .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  213. .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
  214. .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  215. .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
  216. .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  217. .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  218. .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  219. .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  220. .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
  221. .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
  222. .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  223. .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  224. };
  225. fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = {
  226. .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
  227. .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
  228. .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
  229. .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
  230. .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
  231. .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  232. .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
  233. .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
  234. .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
  235. .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
  236. .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
  237. .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
  238. .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
  239. .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
  240. .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
  241. .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
  242. .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
  243. .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  244. .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
  245. .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  246. .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
  247. .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  248. .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  249. .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  250. .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  251. .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
  252. .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
  253. .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  254. .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  255. };
  256. fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
  257. .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  258. .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
  259. .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
  260. .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
  261. .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  262. .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  263. .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
  264. .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
  265. .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
  266. .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
  267. .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
  268. .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
  269. .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
  270. .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
  271. .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
  272. .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
  273. .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
  274. .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  275. .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
  276. .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  277. .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
  278. .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  279. .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  280. .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  281. .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  282. .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
  283. .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
  284. .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  285. .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  286. };
  287. fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
  288. .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
  289. .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
  290. .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
  291. .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
  292. .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
  293. .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  294. .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
  295. .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
  296. .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
  297. .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
  298. .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
  299. .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
  300. .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
  301. .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
  302. .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
  303. .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
  304. .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
  305. .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  306. .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
  307. .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  308. .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
  309. .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  310. .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  311. .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  312. .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  313. .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
  314. .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
  315. .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  316. .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  317. };
  318. fixed_ddr_parm_t fixed_ddr_parm_0[] = {
  319. {750, 850, &ddr_cfg_regs_800},
  320. {850, 950, &ddr_cfg_regs_900},
  321. {950, 1050, &ddr_cfg_regs_1000},
  322. {1050, 1250, &ddr_cfg_regs_1200},
  323. {0, 0, NULL}
  324. };
  325. fixed_ddr_parm_t fixed_ddr_parm_1[] = {
  326. {750, 850, &ddr_cfg_regs_800_2nd},
  327. {850, 950, &ddr_cfg_regs_900_2nd},
  328. {950, 1050, &ddr_cfg_regs_1000_2nd},
  329. {1050, 1250, &ddr_cfg_regs_1200_2nd},
  330. {0, 0, NULL}
  331. };