eth_superhydra.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. * Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  5. */
  6. /*
  7. * This file handles the board muxing between the Fman Ethernet MACs and
  8. * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference
  9. * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
  10. * provided by the standard Freescale four-port SGMII riser card. The 10Gb
  11. * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans
  12. * and 5 1G interfaces and 10G interface per FMan. Based on the options in
  13. * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time.
  14. *
  15. * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
  16. * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
  17. * always the same (0). The value for SGMII depends on which slot the riser is
  18. * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
  19. * the value is based on which slot the XAUI is inserted in.
  20. *
  21. * The SERDES configuration is used to determine where the SGMII and XAUI cards
  22. * exist, and also which Fman's MACs are routed to which PHYs. So for a given
  23. * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
  24. * to PHYs dynamically.
  25. *
  26. *
  27. * This file also updates the device tree in three ways:
  28. *
  29. * 1) The status of each virtual MDIO node that is referenced by an Ethernet
  30. * node is set to "okay".
  31. *
  32. * 2) The phy-handle property of each active Ethernet MAC node is set to the
  33. * appropriate PHY node.
  34. *
  35. * 3) The "mux value" for each virtual MDIO node is set to the correct value,
  36. * if necessary. Some virtual MDIO nodes do not have configurable mux
  37. * values, so those values are hard-coded in the DTS. On the HYDRA board,
  38. * the virtual MDIO node for the SGMII card needs to be updated.
  39. *
  40. * For all this to work, the device tree needs to have the following:
  41. *
  42. * 1) An alias for each PHY node that an Ethernet node could be routed to.
  43. *
  44. * 2) An alias for each real and virtual MDIO node that is disabled by default
  45. * and might need to be enabled, and also might need to have its mux-value
  46. * updated.
  47. */
  48. #include <common.h>
  49. #include <log.h>
  50. #include <net.h>
  51. #include <netdev.h>
  52. #include <asm/fsl_serdes.h>
  53. #include <fm_eth.h>
  54. #include <fsl_mdio.h>
  55. #include <malloc.h>
  56. #include <fdt_support.h>
  57. #include <fsl_dtsec.h>
  58. #include "../common/ngpixis.h"
  59. #include "../common/fman.h"
  60. #ifdef CONFIG_FMAN_ENET
  61. #define BRDCFG1_EMI1_SEL_MASK 0x70
  62. #define BRDCFG1_EMI1_SEL_SLOT1 0x10
  63. #define BRDCFG1_EMI1_SEL_SLOT2 0x20
  64. #define BRDCFG1_EMI1_SEL_SLOT5 0x30
  65. #define BRDCFG1_EMI1_SEL_SLOT6 0x40
  66. #define BRDCFG1_EMI1_SEL_SLOT7 0x50
  67. #define BRDCFG1_EMI1_SEL_SLOT3 0x60
  68. #define BRDCFG1_EMI1_SEL_RGMII 0x00
  69. #define BRDCFG1_EMI1_EN 0x08
  70. #define BRDCFG1_EMI2_SEL_MASK 0x06
  71. #define BRDCFG1_EMI2_SEL_SLOT1 0x00
  72. #define BRDCFG1_EMI2_SEL_SLOT2 0x02
  73. #define BRDCFG2_REG_GPIO_SEL 0x20
  74. /* SGMII */
  75. #define PHY_BASE_ADDR 0x00
  76. #define REGNUM 0x00
  77. #define PORT_NUM_FM1 0x04
  78. #define PORT_NUM_FM2 0x02
  79. /*
  80. * BRDCFG1 mask and value for each MAC
  81. *
  82. * This array contains the BRDCFG1 values (in mask/val format) that route the
  83. * MDIO bus to a particular RGMII or SGMII PHY.
  84. */
  85. static struct {
  86. u8 mask;
  87. u8 val;
  88. } mdio_mux[NUM_FM_PORTS];
  89. /*
  90. * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
  91. * that the mapping must be determined dynamically, or that the lane maps to
  92. * something other than a board slot
  93. */
  94. static u8 lane_to_slot[] = {
  95. 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0
  96. };
  97. /*
  98. * Set the board muxing for a given MAC
  99. *
  100. * The MDIO layer calls this function every time it wants to talk to a PHY.
  101. */
  102. void super_hydra_mux_mdio(u8 mask, u8 val)
  103. {
  104. clrsetbits_8(&pixis->brdcfg1, mask, val);
  105. }
  106. struct super_hydra_mdio {
  107. u8 mask;
  108. u8 val;
  109. struct mii_dev *realbus;
  110. };
  111. static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
  112. int regnum)
  113. {
  114. struct super_hydra_mdio *priv = bus->priv;
  115. super_hydra_mux_mdio(priv->mask, priv->val);
  116. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  117. }
  118. static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
  119. int regnum, u16 value)
  120. {
  121. struct super_hydra_mdio *priv = bus->priv;
  122. super_hydra_mux_mdio(priv->mask, priv->val);
  123. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  124. }
  125. static int super_hydra_mdio_reset(struct mii_dev *bus)
  126. {
  127. struct super_hydra_mdio *priv = bus->priv;
  128. return priv->realbus->reset(priv->realbus);
  129. }
  130. static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val)
  131. {
  132. struct mii_dev *bus = miiphy_get_dev_by_name(name);
  133. struct super_hydra_mdio *priv = bus->priv;
  134. priv->mask = mask;
  135. priv->val = val;
  136. }
  137. static int super_hydra_mdio_init(char *realbusname, char *fakebusname)
  138. {
  139. struct super_hydra_mdio *hmdio;
  140. struct mii_dev *bus = mdio_alloc();
  141. if (!bus) {
  142. printf("Failed to allocate Hydra MDIO bus\n");
  143. return -1;
  144. }
  145. hmdio = malloc(sizeof(*hmdio));
  146. if (!hmdio) {
  147. printf("Failed to allocate Hydra private data\n");
  148. free(bus);
  149. return -1;
  150. }
  151. bus->read = super_hydra_mdio_read;
  152. bus->write = super_hydra_mdio_write;
  153. bus->reset = super_hydra_mdio_reset;
  154. strcpy(bus->name, fakebusname);
  155. hmdio->realbus = miiphy_get_dev_by_name(realbusname);
  156. if (!hmdio->realbus) {
  157. printf("No bus with name %s\n", realbusname);
  158. free(bus);
  159. free(hmdio);
  160. return -1;
  161. }
  162. bus->priv = hmdio;
  163. return mdio_register(bus);
  164. }
  165. /*
  166. * Given the following ...
  167. *
  168. * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
  169. * compatible string and 'addr' physical address)
  170. *
  171. * 2) An Fman port
  172. *
  173. * ... update the phy-handle property of the Ethernet node to point to the
  174. * right PHY. This assumes that we already know the PHY for each port. That
  175. * information is stored in mdio_mux[].
  176. *
  177. * The offset of the Fman Ethernet node is also passed in for convenience, but
  178. * it is not used.
  179. *
  180. * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
  181. * Inside the Fman, "ports" are things that connect to MACs. We only call them
  182. * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
  183. * and ports are the same thing.
  184. */
  185. void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
  186. enum fm_port port, int offset)
  187. {
  188. enum srds_prtcl device;
  189. int lane, slot, phy;
  190. char alias[32];
  191. /* RGMII and XGMII are already mapped correctly in the DTS */
  192. if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
  193. device = serdes_device_from_fm_port(port);
  194. lane = serdes_get_first_lane(device);
  195. slot = lane_to_slot[lane];
  196. phy = fm_info_get_phy_address(port);
  197. sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy);
  198. fdt_set_phy_handle(fdt, compat, addr, alias);
  199. }
  200. }
  201. #define PIXIS_SW2_LANE_23_SEL 0x80
  202. #define PIXIS_SW2_LANE_45_SEL 0x40
  203. #define PIXIS_SW2_LANE_67_SEL_MASK 0x30
  204. #define PIXIS_SW2_LANE_67_SEL_5 0x00
  205. #define PIXIS_SW2_LANE_67_SEL_6 0x20
  206. #define PIXIS_SW2_LANE_67_SEL_7 0x10
  207. #define PIXIS_SW2_LANE_8_SEL 0x08
  208. #define PIXIS_SW2_LANE_1617_SEL 0x04
  209. #define PIXIS_SW11_LANE_9_SEL 0x04
  210. /*
  211. * Initialize the lane_to_slot[] array.
  212. *
  213. * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
  214. * slots is hard-coded. On the Hydra board, however, the mapping is controlled
  215. * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
  216. * initialized.
  217. */
  218. static void initialize_lane_to_slot(void)
  219. {
  220. u8 sw2 = in_8(&PIXIS_SW(2));
  221. /* SW11 appears in the programming model as SW9 */
  222. u8 sw11 = in_8(&PIXIS_SW(9));
  223. lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
  224. lane_to_slot[3] = lane_to_slot[2];
  225. lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
  226. lane_to_slot[5] = lane_to_slot[4];
  227. switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
  228. case PIXIS_SW2_LANE_67_SEL_5:
  229. lane_to_slot[6] = 5;
  230. break;
  231. case PIXIS_SW2_LANE_67_SEL_6:
  232. lane_to_slot[6] = 6;
  233. break;
  234. case PIXIS_SW2_LANE_67_SEL_7:
  235. lane_to_slot[6] = 7;
  236. break;
  237. }
  238. lane_to_slot[7] = lane_to_slot[6];
  239. lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
  240. lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3;
  241. lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
  242. lane_to_slot[17] = lane_to_slot[16];
  243. }
  244. #endif /* #ifdef CONFIG_FMAN_ENET */
  245. /*
  246. * Configure the status for the virtual MDIO nodes
  247. *
  248. * Rather than create the virtual MDIO nodes from scratch for each active
  249. * virtual MDIO, we expect the DTS to have the nodes defined already, and we
  250. * only enable the ones that are actually active.
  251. *
  252. * We assume that the DTS already hard-codes the status for all the
  253. * virtual MDIO nodes to "disabled", so all we need to do is enable the
  254. * active ones.
  255. */
  256. void fdt_fixup_board_enet(void *fdt)
  257. {
  258. #ifdef CONFIG_FMAN_ENET
  259. enum fm_port i;
  260. int lane, slot;
  261. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  262. int idx = i - FM1_DTSEC1;
  263. switch (fm_info_get_enet_if(i)) {
  264. case PHY_INTERFACE_MODE_SGMII:
  265. lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
  266. if (lane >= 0) {
  267. char alias[32];
  268. slot = lane_to_slot[lane];
  269. sprintf(alias, "hydra_sg_slot%u", slot);
  270. fdt_status_okay_by_alias(fdt, alias);
  271. debug("Enabled MDIO node %s (slot %i)\n",
  272. alias, slot);
  273. }
  274. break;
  275. case PHY_INTERFACE_MODE_RGMII:
  276. case PHY_INTERFACE_MODE_RGMII_TXID:
  277. case PHY_INTERFACE_MODE_RGMII_RXID:
  278. case PHY_INTERFACE_MODE_RGMII_ID:
  279. fdt_status_okay_by_alias(fdt, "hydra_rg");
  280. debug("Enabled MDIO node hydra_rg\n");
  281. break;
  282. default:
  283. break;
  284. }
  285. }
  286. lane = serdes_get_first_lane(XAUI_FM1);
  287. if (lane >= 0) {
  288. char alias[32];
  289. slot = lane_to_slot[lane];
  290. sprintf(alias, "hydra_xg_slot%u", slot);
  291. fdt_status_okay_by_alias(fdt, alias);
  292. debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
  293. }
  294. #if CONFIG_SYS_NUM_FMAN == 2
  295. for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
  296. int idx = i - FM2_DTSEC1;
  297. switch (fm_info_get_enet_if(i)) {
  298. case PHY_INTERFACE_MODE_SGMII:
  299. lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
  300. if (lane >= 0) {
  301. char alias[32];
  302. slot = lane_to_slot[lane];
  303. sprintf(alias, "hydra_sg_slot%u", slot);
  304. fdt_status_okay_by_alias(fdt, alias);
  305. debug("Enabled MDIO node %s (slot %i)\n",
  306. alias, slot);
  307. }
  308. break;
  309. case PHY_INTERFACE_MODE_RGMII:
  310. case PHY_INTERFACE_MODE_RGMII_TXID:
  311. case PHY_INTERFACE_MODE_RGMII_RXID:
  312. case PHY_INTERFACE_MODE_RGMII_ID:
  313. fdt_status_okay_by_alias(fdt, "hydra_rg");
  314. debug("Enabled MDIO node hydra_rg\n");
  315. break;
  316. default:
  317. break;
  318. }
  319. }
  320. lane = serdes_get_first_lane(XAUI_FM2);
  321. if (lane >= 0) {
  322. char alias[32];
  323. slot = lane_to_slot[lane];
  324. sprintf(alias, "hydra_xg_slot%u", slot);
  325. fdt_status_okay_by_alias(fdt, alias);
  326. debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
  327. }
  328. #endif /* CONFIG_SYS_NUM_FMAN == 2 */
  329. #endif /* CONFIG_FMAN_ENET */
  330. }
  331. /*
  332. * Mapping of SerDes Protocol to MDIO MUX value and PHY address.
  333. *
  334. * Fman 1:
  335. * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
  336. * Mux Phy | Mux Phy | Mux Phy | Mux Phy
  337. * Value Addr | Value Addr | Value Addr | Value Addr
  338. * 0x00 2 1c | 2 1d | 2 1e | 2 1f
  339. * 0x01 | | 6 1c |
  340. * 0x02 | | 3 1c | 3 1d
  341. * 0x03 2 1c | 2 1d | 2 1e | 2 1f
  342. * 0x04 2 1c | 2 1d | 2 1e | 2 1f
  343. * 0x05 | | 3 1c | 3 1d
  344. * 0x06 2 1c | 2 1d | 2 1e | 2 1f
  345. * 0x07 | | 6 1c |
  346. * 0x11 2 1c | 2 1d | 2 1e | 2 1f
  347. * 0x2a 2 | | 2 1e | 2 1f
  348. * 0x34 6 1c | 6 1d | 4 1e | 4 1f
  349. * 0x35 | | 3 1c | 3 1d
  350. * 0x36 6 1c | 6 1d | 4 1e | 4 1f
  351. * | | |
  352. * Fman 2: | | |
  353. * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
  354. * EMI1 | EMI1 | EMI1 | EMI1
  355. * Mux Phy | Mux Phy | Mux Phy | Mux Phy
  356. * Value Addr | Value Addr | Value Addr | Value Addr
  357. * 0x00 | | 6 1c | 6 1d
  358. * 0x01 | | |
  359. * 0x02 | | 6 1c | 6 1d
  360. * 0x03 3 1c | 3 1d | 6 1c | 6 1d
  361. * 0x04 3 1c | 3 1d | 6 1c | 6 1d
  362. * 0x05 | | 6 1c | 6 1d
  363. * 0x06 | | 6 1c | 6 1d
  364. * 0x07 | | |
  365. * 0x11 | | |
  366. * 0x2a | | |
  367. * 0x34 | | |
  368. * 0x35 | | |
  369. * 0x36 | | |
  370. */
  371. int board_eth_init(struct bd_info *bis)
  372. {
  373. #ifdef CONFIG_FMAN_ENET
  374. struct fsl_pq_mdio_info dtsec_mdio_info;
  375. struct tgec_mdio_info tgec_mdio_info;
  376. unsigned int i, slot;
  377. int lane;
  378. struct mii_dev *bus;
  379. int qsgmii;
  380. int phy_real_addr;
  381. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  382. int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
  383. FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
  384. printf("Initializing Fman\n");
  385. initialize_lane_to_slot();
  386. /* We want to use the PIXIS to configure MUX routing, not GPIOs. */
  387. setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
  388. memset(mdio_mux, 0, sizeof(mdio_mux));
  389. dtsec_mdio_info.regs =
  390. (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
  391. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  392. /* Register the real 1G MDIO bus */
  393. fsl_pq_mdio_init(bis, &dtsec_mdio_info);
  394. tgec_mdio_info.regs =
  395. (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  396. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  397. /* Register the real 10G MDIO bus */
  398. fm_tgec_mdio_init(bis, &tgec_mdio_info);
  399. /* Register the three virtual MDIO front-ends */
  400. super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
  401. "SUPER_HYDRA_RGMII_MDIO");
  402. super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
  403. "SUPER_HYDRA_FM1_SGMII_MDIO");
  404. super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
  405. "SUPER_HYDRA_FM2_SGMII_MDIO");
  406. super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
  407. "SUPER_HYDRA_FM3_SGMII_MDIO");
  408. super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
  409. "SUPER_HYDRA_FM1_TGEC_MDIO");
  410. super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
  411. "SUPER_HYDRA_FM2_TGEC_MDIO");
  412. /*
  413. * Program the DTSEC PHY addresses assuming that they are all SGMII.
  414. * For any DTSEC that's RGMII, we'll override its PHY address later.
  415. * We assume that DTSEC5 is only used for RGMII.
  416. */
  417. fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
  418. fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
  419. fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
  420. #if (CONFIG_SYS_NUM_FMAN == 2)
  421. fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
  422. fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
  423. fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
  424. fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
  425. fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
  426. #endif
  427. switch (srds_prtcl) {
  428. case 0:
  429. case 3:
  430. case 4:
  431. case 6:
  432. case 0x11:
  433. case 0x2a:
  434. case 0x34:
  435. case 0x36:
  436. fm_info_set_phy_address(FM1_DTSEC3,
  437. CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
  438. fm_info_set_phy_address(FM1_DTSEC4,
  439. CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
  440. break;
  441. case 1:
  442. case 2:
  443. case 5:
  444. case 7:
  445. case 0x35:
  446. fm_info_set_phy_address(FM1_DTSEC3,
  447. CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
  448. fm_info_set_phy_address(FM1_DTSEC4,
  449. CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
  450. break;
  451. default:
  452. printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl);
  453. break;
  454. }
  455. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  456. int idx = i - FM1_DTSEC1;
  457. switch (fm_info_get_enet_if(i)) {
  458. case PHY_INTERFACE_MODE_SGMII:
  459. lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
  460. if (lane < 0)
  461. break;
  462. slot = lane_to_slot[lane];
  463. mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
  464. debug("FM1@DTSEC%u expects SGMII in slot %u\n",
  465. idx + 1, slot);
  466. switch (slot) {
  467. case 1:
  468. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
  469. BRDCFG1_EMI1_EN;
  470. break;
  471. case 2:
  472. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
  473. BRDCFG1_EMI1_EN;
  474. break;
  475. case 3:
  476. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
  477. BRDCFG1_EMI1_EN;
  478. break;
  479. case 5:
  480. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
  481. BRDCFG1_EMI1_EN;
  482. break;
  483. case 6:
  484. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
  485. BRDCFG1_EMI1_EN;
  486. break;
  487. case 7:
  488. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
  489. BRDCFG1_EMI1_EN;
  490. break;
  491. };
  492. super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO",
  493. mdio_mux[i].mask, mdio_mux[i].val);
  494. fm_info_set_mdio(i,
  495. miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
  496. break;
  497. case PHY_INTERFACE_MODE_RGMII:
  498. case PHY_INTERFACE_MODE_RGMII_TXID:
  499. case PHY_INTERFACE_MODE_RGMII_RXID:
  500. case PHY_INTERFACE_MODE_RGMII_ID:
  501. /*
  502. * FM1 DTSEC5 is routed via EC1 to the first on-board
  503. * RGMII port. FM2 DTSEC5 is routed via EC2 to the
  504. * second on-board RGMII port. The other DTSECs cannot
  505. * be routed to RGMII.
  506. */
  507. debug("FM1@DTSEC%u is RGMII at address %u\n",
  508. idx + 1, 0);
  509. fm_info_set_phy_address(i, 0);
  510. mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
  511. mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
  512. BRDCFG1_EMI1_EN;
  513. super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
  514. mdio_mux[i].mask, mdio_mux[i].val);
  515. fm_info_set_mdio(i,
  516. miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
  517. break;
  518. case PHY_INTERFACE_MODE_NONE:
  519. fm_info_set_phy_address(i, 0);
  520. break;
  521. default:
  522. printf("Fman1: DTSEC%u set to unknown interface %i\n",
  523. idx + 1, fm_info_get_enet_if(i));
  524. fm_info_set_phy_address(i, 0);
  525. break;
  526. }
  527. }
  528. bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO");
  529. qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM);
  530. if (qsgmii) {
  531. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) {
  532. if (fm_info_get_enet_if(i) ==
  533. PHY_INTERFACE_MODE_SGMII) {
  534. phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1;
  535. fm_info_set_phy_address(i, phy_real_addr);
  536. }
  537. }
  538. switch (srds_prtcl) {
  539. case 0x00:
  540. case 0x03:
  541. case 0x04:
  542. case 0x06:
  543. case 0x11:
  544. case 0x2a:
  545. case 0x34:
  546. case 0x36:
  547. fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2);
  548. fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3);
  549. break;
  550. case 0x01:
  551. case 0x02:
  552. case 0x05:
  553. case 0x07:
  554. case 0x35:
  555. fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0);
  556. fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
  557. break;
  558. default:
  559. break;
  560. }
  561. }
  562. /*
  563. * For 10G, we only support one XAUI card per Fman. If present, then we
  564. * force its routing and never touch those bits again, which removes the
  565. * need for Linux to do any muxing. This works because of the way
  566. * BRDCFG1 is defined, but it's a bit hackish.
  567. *
  568. * The PHY address for the XAUI card depends on which slot it's in. The
  569. * macros we use imply that the PHY address is based on which FM, but
  570. * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
  571. * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
  572. * check the actual slot and just use the macros as-is, even though
  573. * the P3041 and P5020 only have one Fman.
  574. */
  575. lane = serdes_get_first_lane(XAUI_FM1);
  576. if (lane >= 0) {
  577. debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
  578. mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
  579. mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2;
  580. super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO",
  581. mdio_mux[i].mask, mdio_mux[i].val);
  582. }
  583. fm_info_set_mdio(FM1_10GEC1,
  584. miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO"));
  585. #if (CONFIG_SYS_NUM_FMAN == 2)
  586. for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
  587. int idx = i - FM2_DTSEC1;
  588. switch (fm_info_get_enet_if(i)) {
  589. case PHY_INTERFACE_MODE_SGMII:
  590. lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
  591. if (lane < 0)
  592. break;
  593. slot = lane_to_slot[lane];
  594. mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
  595. debug("FM2@DTSEC%u expects SGMII in slot %u\n",
  596. idx + 1, slot);
  597. switch (slot) {
  598. case 1:
  599. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
  600. BRDCFG1_EMI1_EN;
  601. break;
  602. case 2:
  603. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
  604. BRDCFG1_EMI1_EN;
  605. break;
  606. case 3:
  607. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
  608. BRDCFG1_EMI1_EN;
  609. break;
  610. case 5:
  611. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
  612. BRDCFG1_EMI1_EN;
  613. break;
  614. case 6:
  615. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
  616. BRDCFG1_EMI1_EN;
  617. break;
  618. case 7:
  619. mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
  620. BRDCFG1_EMI1_EN;
  621. break;
  622. };
  623. if (i == FM2_DTSEC1 || i == FM2_DTSEC2) {
  624. super_hydra_mdio_set_mux(
  625. "SUPER_HYDRA_FM3_SGMII_MDIO",
  626. mdio_mux[i].mask,
  627. mdio_mux[i].val);
  628. fm_info_set_mdio(i, miiphy_get_dev_by_name(
  629. "SUPER_HYDRA_FM3_SGMII_MDIO"));
  630. } else {
  631. super_hydra_mdio_set_mux(
  632. "SUPER_HYDRA_FM2_SGMII_MDIO",
  633. mdio_mux[i].mask,
  634. mdio_mux[i].val);
  635. fm_info_set_mdio(i, miiphy_get_dev_by_name(
  636. "SUPER_HYDRA_FM2_SGMII_MDIO"));
  637. }
  638. break;
  639. case PHY_INTERFACE_MODE_RGMII:
  640. case PHY_INTERFACE_MODE_RGMII_TXID:
  641. case PHY_INTERFACE_MODE_RGMII_RXID:
  642. case PHY_INTERFACE_MODE_RGMII_ID:
  643. /*
  644. * FM1 DTSEC5 is routed via EC1 to the first on-board
  645. * RGMII port. FM2 DTSEC5 is routed via EC2 to the
  646. * second on-board RGMII port. The other DTSECs cannot
  647. * be routed to RGMII.
  648. */
  649. debug("FM2@DTSEC%u is RGMII at address %u\n",
  650. idx + 1, 1);
  651. fm_info_set_phy_address(i, 1);
  652. mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
  653. mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
  654. BRDCFG1_EMI1_EN;
  655. super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
  656. mdio_mux[i].mask, mdio_mux[i].val);
  657. fm_info_set_mdio(i,
  658. miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
  659. break;
  660. case PHY_INTERFACE_MODE_NONE:
  661. fm_info_set_phy_address(i, 0);
  662. break;
  663. default:
  664. printf("Fman2: DTSEC%u set to unknown interface %i\n",
  665. idx + 1, fm_info_get_enet_if(i));
  666. fm_info_set_phy_address(i, 0);
  667. break;
  668. }
  669. }
  670. bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO");
  671. set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR);
  672. bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO");
  673. set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR);
  674. /*
  675. * For 10G, we only support one XAUI card per Fman. If present, then we
  676. * force its routing and never touch those bits again, which removes the
  677. * need for Linux to do any muxing. This works because of the way
  678. * BRDCFG1 is defined, but it's a bit hackish.
  679. *
  680. * The PHY address for the XAUI card depends on which slot it's in. The
  681. * macros we use imply that the PHY address is based on which FM, but
  682. * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
  683. * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
  684. * check the actual slot and just use the macros as-is, even though
  685. * the P3041 and P5020 only have one Fman.
  686. */
  687. lane = serdes_get_first_lane(XAUI_FM2);
  688. if (lane >= 0) {
  689. debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
  690. mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
  691. mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1;
  692. super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO",
  693. mdio_mux[i].mask, mdio_mux[i].val);
  694. }
  695. fm_info_set_mdio(FM2_10GEC1,
  696. miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO"));
  697. #endif
  698. cpu_eth_init(bis);
  699. #endif
  700. return pci_eth_init(bis);
  701. }