eth_p4080.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <fdt_support.h>
  8. #include <net.h>
  9. #include <netdev.h>
  10. #include <asm/mmu.h>
  11. #include <asm/processor.h>
  12. #include <asm/cache.h>
  13. #include <asm/immap_85xx.h>
  14. #include <asm/fsl_law.h>
  15. #include <fsl_ddr_sdram.h>
  16. #include <asm/fsl_serdes.h>
  17. #include <asm/fsl_portals.h>
  18. #include <asm/fsl_liodn.h>
  19. #include <malloc.h>
  20. #include <fm_eth.h>
  21. #include <fsl_mdio.h>
  22. #include <miiphy.h>
  23. #include <phy.h>
  24. #include <linux/delay.h>
  25. #include "../common/ngpixis.h"
  26. #include "../common/fman.h"
  27. #include <fsl_dtsec.h>
  28. #define EMI_NONE 0xffffffff
  29. #define EMI_MASK 0xf0000000
  30. #define EMI1_RGMII 0x0
  31. #define EMI1_SLOT3 0x80000000 /* bank1 EFGH */
  32. #define EMI1_SLOT4 0x40000000 /* bank2 ABCD */
  33. #define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */
  34. #define EMI2_SLOT4 0x10000000 /* bank2 ABCD */
  35. #define EMI2_SLOT5 0x30000000 /* bank3 ABCD */
  36. #define EMI1_MASK 0xc0000000
  37. #define EMI2_MASK 0x30000000
  38. #define PHY_BASE_ADDR 0x00
  39. #define PHY_BASE_ADDR_SLOT5 0x10
  40. static int mdio_mux[NUM_FM_PORTS];
  41. static char *mdio_names[16] = {
  42. "P4080DS_MDIO0",
  43. "P4080DS_MDIO1",
  44. NULL,
  45. "P4080DS_MDIO3",
  46. "P4080DS_MDIO4",
  47. NULL, NULL, NULL,
  48. "P4080DS_MDIO8",
  49. NULL, NULL, NULL,
  50. "P4080DS_MDIO12",
  51. NULL, NULL, NULL,
  52. };
  53. /*
  54. * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
  55. * that the mapping must be determined dynamically, or that the lane maps to
  56. * something other than a board slot.
  57. */
  58. static u8 lane_to_slot[] = {
  59. 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
  60. };
  61. static char *p4080ds_mdio_name_for_muxval(u32 muxval)
  62. {
  63. return mdio_names[(muxval & EMI_MASK) >> 28];
  64. }
  65. struct mii_dev *mii_dev_for_muxval(u32 muxval)
  66. {
  67. struct mii_dev *bus;
  68. char *name = p4080ds_mdio_name_for_muxval(muxval);
  69. if (!name) {
  70. printf("No bus for muxval %x\n", muxval);
  71. return NULL;
  72. }
  73. bus = miiphy_get_dev_by_name(name);
  74. if (!bus) {
  75. printf("No bus by name %s\n", name);
  76. return NULL;
  77. }
  78. return bus;
  79. }
  80. #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
  81. int board_phy_config(struct phy_device *phydev)
  82. {
  83. if (phydev->drv->config)
  84. phydev->drv->config(phydev);
  85. if (phydev->drv->uid == PHY_UID_TN2020) {
  86. unsigned long timeout = 1 * 1000; /* 1 seconds */
  87. enum srds_prtcl device;
  88. /*
  89. * Wait for the XAUI to come out of reset. This is when it
  90. * starts transmitting alignment signals.
  91. */
  92. while (--timeout) {
  93. int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
  94. if (reg < 0) {
  95. printf("TN2020: Error reading from PHY at "
  96. "address %u\n", phydev->addr);
  97. break;
  98. }
  99. /*
  100. * Note that we've never actually seen
  101. * MDIO_CTRL1_RESET set to 1.
  102. */
  103. if ((reg & MDIO_CTRL1_RESET) == 0)
  104. break;
  105. udelay(1000);
  106. }
  107. if (!timeout) {
  108. printf("TN2020: Timeout waiting for PHY at address %u "
  109. " to reset.\n", phydev->addr);
  110. }
  111. switch (phydev->addr) {
  112. case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
  113. device = XAUI_FM1;
  114. break;
  115. case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
  116. device = XAUI_FM2;
  117. break;
  118. default:
  119. device = NONE;
  120. }
  121. serdes_reset_rx(device);
  122. }
  123. return 0;
  124. }
  125. #endif
  126. struct p4080ds_mdio {
  127. u32 muxval;
  128. struct mii_dev *realbus;
  129. };
  130. static void p4080ds_mux_mdio(u32 muxval)
  131. {
  132. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  133. uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK);
  134. gpioval |= muxval;
  135. out_be32(&pgpio->gpdat, gpioval);
  136. }
  137. static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad,
  138. int regnum)
  139. {
  140. struct p4080ds_mdio *priv = bus->priv;
  141. p4080ds_mux_mdio(priv->muxval);
  142. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  143. }
  144. static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad,
  145. int regnum, u16 value)
  146. {
  147. struct p4080ds_mdio *priv = bus->priv;
  148. p4080ds_mux_mdio(priv->muxval);
  149. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  150. }
  151. static int p4080ds_mdio_reset(struct mii_dev *bus)
  152. {
  153. struct p4080ds_mdio *priv = bus->priv;
  154. return priv->realbus->reset(priv->realbus);
  155. }
  156. static int p4080ds_mdio_init(char *realbusname, u32 muxval)
  157. {
  158. struct p4080ds_mdio *pmdio;
  159. struct mii_dev *bus = mdio_alloc();
  160. if (!bus) {
  161. printf("Failed to allocate P4080DS MDIO bus\n");
  162. return -1;
  163. }
  164. pmdio = malloc(sizeof(*pmdio));
  165. if (!pmdio) {
  166. printf("Failed to allocate P4080DS private data\n");
  167. free(bus);
  168. return -1;
  169. }
  170. bus->read = p4080ds_mdio_read;
  171. bus->write = p4080ds_mdio_write;
  172. bus->reset = p4080ds_mdio_reset;
  173. sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval));
  174. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  175. if (!pmdio->realbus) {
  176. printf("No bus with name %s\n", realbusname);
  177. free(bus);
  178. free(pmdio);
  179. return -1;
  180. }
  181. pmdio->muxval = muxval;
  182. bus->priv = pmdio;
  183. return mdio_register(bus);
  184. }
  185. void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
  186. enum fm_port port, int offset)
  187. {
  188. if (mdio_mux[port] == EMI1_RGMII)
  189. fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
  190. if (mdio_mux[port] == EMI1_SLOT3) {
  191. int idx = port - FM2_DTSEC1 + 5;
  192. char phy[16];
  193. sprintf(phy, "phy%d_slot3", idx);
  194. fdt_set_phy_handle(blob, prop, pa, phy);
  195. }
  196. }
  197. void fdt_fixup_board_enet(void *fdt)
  198. {
  199. int i;
  200. /*
  201. * P4080DS can be configured in many different ways, supporting a number
  202. * of combinations of ethernet devices and phy types. In order to
  203. * have just one device tree for all of those configurations, we fix up
  204. * the tree here. By default, the device tree configures FM1 and FM2
  205. * for SGMII, and configures XAUI on both 10G interfaces. So we have
  206. * a number of different variables to track:
  207. *
  208. * 1) Whether the device is configured at all. Whichever devices are
  209. * not enabled should be disabled by setting the "status" property
  210. * to "disabled".
  211. * 2) What the PHY interface is. If this is an RGMII connection,
  212. * we should change the "phy-connection-type" property to
  213. * "rgmii"
  214. * 3) Which PHY is being used. Because the MDIO buses are muxed,
  215. * we need to redirect the "phy-handle" property to point at the
  216. * PHY on the right slot/bus.
  217. */
  218. /* We've got six MDIO nodes that may or may not need to exist */
  219. fdt_status_disabled_by_alias(fdt, "emi1_slot3");
  220. fdt_status_disabled_by_alias(fdt, "emi1_slot4");
  221. fdt_status_disabled_by_alias(fdt, "emi1_slot5");
  222. fdt_status_disabled_by_alias(fdt, "emi2_slot4");
  223. fdt_status_disabled_by_alias(fdt, "emi2_slot5");
  224. for (i = 0; i < NUM_FM_PORTS; i++) {
  225. switch (mdio_mux[i]) {
  226. case EMI1_SLOT3:
  227. fdt_status_okay_by_alias(fdt, "emi1_slot3");
  228. break;
  229. case EMI1_SLOT4:
  230. fdt_status_okay_by_alias(fdt, "emi1_slot4");
  231. break;
  232. case EMI1_SLOT5:
  233. fdt_status_okay_by_alias(fdt, "emi1_slot5");
  234. break;
  235. case EMI2_SLOT4:
  236. fdt_status_okay_by_alias(fdt, "emi2_slot4");
  237. break;
  238. case EMI2_SLOT5:
  239. fdt_status_okay_by_alias(fdt, "emi2_slot5");
  240. break;
  241. }
  242. }
  243. }
  244. int board_eth_init(struct bd_info *bis)
  245. {
  246. #ifdef CONFIG_FMAN_ENET
  247. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  248. int i;
  249. struct fsl_pq_mdio_info dtsec_mdio_info;
  250. struct tgec_mdio_info tgec_mdio_info;
  251. struct mii_dev *bus;
  252. /* Initialize the mdio_mux array so we can recognize empty elements */
  253. for (i = 0; i < NUM_FM_PORTS; i++)
  254. mdio_mux[i] = EMI_NONE;
  255. /* The first 4 GPIOs are outputs to control MDIO bus muxing */
  256. out_be32(&pgpio->gpdir, EMI_MASK);
  257. dtsec_mdio_info.regs =
  258. (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
  259. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  260. /* Register the 1G MDIO bus */
  261. fsl_pq_mdio_init(bis, &dtsec_mdio_info);
  262. tgec_mdio_info.regs =
  263. (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  264. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  265. /* Register the 10G MDIO bus */
  266. fm_tgec_mdio_init(bis, &tgec_mdio_info);
  267. /* Register the 6 muxing front-ends to the MDIO buses */
  268. p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
  269. p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
  270. p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
  271. p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
  272. p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
  273. p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
  274. fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
  275. fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
  276. fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
  277. fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
  278. fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
  279. #if (CONFIG_SYS_NUM_FMAN == 2)
  280. fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
  281. fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
  282. fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR);
  283. fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR);
  284. fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
  285. #endif
  286. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  287. int idx = i - FM1_DTSEC1, lane, slot;
  288. switch (fm_info_get_enet_if(i)) {
  289. case PHY_INTERFACE_MODE_SGMII:
  290. lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
  291. if (lane < 0)
  292. break;
  293. slot = lane_to_slot[lane];
  294. switch (slot) {
  295. case 3:
  296. mdio_mux[i] = EMI1_SLOT3;
  297. fm_info_set_mdio(i,
  298. mii_dev_for_muxval(mdio_mux[i]));
  299. break;
  300. case 4:
  301. mdio_mux[i] = EMI1_SLOT4;
  302. fm_info_set_mdio(i,
  303. mii_dev_for_muxval(mdio_mux[i]));
  304. break;
  305. case 5:
  306. mdio_mux[i] = EMI1_SLOT5;
  307. fm_info_set_mdio(i,
  308. mii_dev_for_muxval(mdio_mux[i]));
  309. break;
  310. };
  311. break;
  312. case PHY_INTERFACE_MODE_RGMII:
  313. case PHY_INTERFACE_MODE_RGMII_TXID:
  314. case PHY_INTERFACE_MODE_RGMII_RXID:
  315. case PHY_INTERFACE_MODE_RGMII_ID:
  316. fm_info_set_phy_address(i, 0);
  317. mdio_mux[i] = EMI1_RGMII;
  318. fm_info_set_mdio(i,
  319. mii_dev_for_muxval(mdio_mux[i]));
  320. break;
  321. default:
  322. break;
  323. }
  324. }
  325. bus = mii_dev_for_muxval(EMI1_SLOT5);
  326. set_sgmii_phy(bus, FM1_DTSEC1,
  327. CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5);
  328. for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  329. int idx = i - FM1_10GEC1, lane, slot;
  330. switch (fm_info_get_enet_if(i)) {
  331. case PHY_INTERFACE_MODE_XGMII:
  332. lane = serdes_get_first_lane(XAUI_FM1 + idx);
  333. if (lane < 0)
  334. break;
  335. slot = lane_to_slot[lane];
  336. switch (slot) {
  337. case 4:
  338. mdio_mux[i] = EMI2_SLOT4;
  339. fm_info_set_mdio(i,
  340. mii_dev_for_muxval(mdio_mux[i]));
  341. break;
  342. case 5:
  343. mdio_mux[i] = EMI2_SLOT5;
  344. fm_info_set_mdio(i,
  345. mii_dev_for_muxval(mdio_mux[i]));
  346. break;
  347. };
  348. break;
  349. default:
  350. break;
  351. }
  352. }
  353. #if (CONFIG_SYS_NUM_FMAN == 2)
  354. for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
  355. int idx = i - FM2_DTSEC1, lane, slot;
  356. switch (fm_info_get_enet_if(i)) {
  357. case PHY_INTERFACE_MODE_SGMII:
  358. lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
  359. if (lane < 0)
  360. break;
  361. slot = lane_to_slot[lane];
  362. switch (slot) {
  363. case 3:
  364. mdio_mux[i] = EMI1_SLOT3;
  365. fm_info_set_mdio(i,
  366. mii_dev_for_muxval(mdio_mux[i]));
  367. break;
  368. case 4:
  369. mdio_mux[i] = EMI1_SLOT4;
  370. fm_info_set_mdio(i,
  371. mii_dev_for_muxval(mdio_mux[i]));
  372. break;
  373. case 5:
  374. mdio_mux[i] = EMI1_SLOT5;
  375. fm_info_set_mdio(i,
  376. mii_dev_for_muxval(mdio_mux[i]));
  377. break;
  378. };
  379. break;
  380. case PHY_INTERFACE_MODE_RGMII:
  381. case PHY_INTERFACE_MODE_RGMII_TXID:
  382. case PHY_INTERFACE_MODE_RGMII_RXID:
  383. case PHY_INTERFACE_MODE_RGMII_ID:
  384. fm_info_set_phy_address(i, 0);
  385. mdio_mux[i] = EMI1_RGMII;
  386. fm_info_set_mdio(i,
  387. mii_dev_for_muxval(mdio_mux[i]));
  388. break;
  389. default:
  390. break;
  391. }
  392. }
  393. bus = mii_dev_for_muxval(EMI1_SLOT3);
  394. set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
  395. bus = mii_dev_for_muxval(EMI1_SLOT4);
  396. set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
  397. for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
  398. int idx = i - FM2_10GEC1, lane, slot;
  399. switch (fm_info_get_enet_if(i)) {
  400. case PHY_INTERFACE_MODE_XGMII:
  401. lane = serdes_get_first_lane(XAUI_FM2 + idx);
  402. if (lane < 0)
  403. break;
  404. slot = lane_to_slot[lane];
  405. switch (slot) {
  406. case 4:
  407. mdio_mux[i] = EMI2_SLOT4;
  408. fm_info_set_mdio(i,
  409. mii_dev_for_muxval(mdio_mux[i]));
  410. break;
  411. case 5:
  412. mdio_mux[i] = EMI2_SLOT5;
  413. fm_info_set_mdio(i,
  414. mii_dev_for_muxval(mdio_mux[i]));
  415. break;
  416. };
  417. break;
  418. default:
  419. break;
  420. }
  421. }
  422. #endif
  423. cpu_eth_init(bis);
  424. #endif /* CONFIG_FMAN_ENET */
  425. return pci_eth_init(bis);
  426. }