ddr.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <hwconfig.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <vsprintf.h>
  11. #include <asm/mmu.h>
  12. #include <fsl_ddr_sdram.h>
  13. #include <fsl_ddr_dimm_params.h>
  14. #include <asm/fsl_law.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /*
  17. * Fixed sdram init -- doesn't use serial presence detect.
  18. */
  19. extern fixed_ddr_parm_t fixed_ddr_parm_0[];
  20. #if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
  21. extern fixed_ddr_parm_t fixed_ddr_parm_1[];
  22. #endif
  23. phys_size_t fixed_sdram(void)
  24. {
  25. int i;
  26. char buf[32];
  27. fsl_ddr_cfg_regs_t ddr_cfg_regs;
  28. phys_size_t ddr_size;
  29. unsigned int lawbar1_target_id;
  30. ulong ddr_freq, ddr_freq_mhz;
  31. ddr_freq = get_ddr_freq(0);
  32. ddr_freq_mhz = ddr_freq / 1000000;
  33. printf("Configuring DDR for %s MT/s data rate\n",
  34. strmhz(buf, ddr_freq));
  35. for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
  36. if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
  37. (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
  38. memcpy(&ddr_cfg_regs,
  39. fixed_ddr_parm_0[i].ddr_settings,
  40. sizeof(ddr_cfg_regs));
  41. break;
  42. }
  43. }
  44. if (fixed_ddr_parm_0[i].max_freq == 0)
  45. panic("Unsupported DDR data rate %s MT/s data rate\n",
  46. strmhz(buf, ddr_freq));
  47. ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  48. ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
  49. fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
  50. #if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
  51. memcpy(&ddr_cfg_regs,
  52. fixed_ddr_parm_1[i].ddr_settings,
  53. sizeof(ddr_cfg_regs));
  54. ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
  55. fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0);
  56. #endif
  57. /*
  58. * setup laws for DDR. If not interleaving, presuming half memory on
  59. * DDR1 and the other half on DDR2
  60. */
  61. if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
  62. if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  63. ddr_size,
  64. LAW_TRGT_IF_DDR_INTRLV) < 0) {
  65. printf("ERROR setting Local Access Windows for DDR\n");
  66. return 0;
  67. }
  68. } else {
  69. #if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
  70. /* We require both controllers have identical DIMMs */
  71. lawbar1_target_id = LAW_TRGT_IF_DDR_1;
  72. if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  73. ddr_size / 2,
  74. lawbar1_target_id) < 0) {
  75. printf("ERROR setting Local Access Windows for DDR\n");
  76. return 0;
  77. }
  78. lawbar1_target_id = LAW_TRGT_IF_DDR_2;
  79. if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
  80. ddr_size / 2,
  81. lawbar1_target_id) < 0) {
  82. printf("ERROR setting Local Access Windows for DDR\n");
  83. return 0;
  84. }
  85. #else
  86. lawbar1_target_id = LAW_TRGT_IF_DDR_1;
  87. if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  88. ddr_size,
  89. lawbar1_target_id) < 0) {
  90. printf("ERROR setting Local Access Windows for DDR\n");
  91. return 0;
  92. }
  93. #endif
  94. }
  95. return ddr_size;
  96. }
  97. struct board_specific_parameters {
  98. u32 n_ranks;
  99. u32 datarate_mhz_high;
  100. u32 clk_adjust;
  101. u32 wrlvl_start;
  102. u32 cpo;
  103. u32 write_data_delay;
  104. u32 force_2t;
  105. };
  106. /*
  107. * This table contains all valid speeds we want to override with board
  108. * specific parameters. datarate_mhz_high values need to be in ascending order
  109. * for each n_ranks group.
  110. */
  111. static const struct board_specific_parameters udimm0[] = {
  112. /*
  113. * memory controller 0
  114. * num| hi| clk| wrlvl | cpo |wrdata|2T
  115. * ranks| mhz|adjst| start | |delay |
  116. */
  117. {4, 850, 4, 6, 0xff, 2, 0},
  118. {4, 950, 5, 7, 0xff, 2, 0},
  119. {4, 1050, 5, 8, 0xff, 2, 0},
  120. {4, 1250, 5, 10, 0xff, 2, 0},
  121. {4, 1350, 5, 11, 0xff, 2, 0},
  122. {4, 1666, 5, 12, 0xff, 2, 0},
  123. {2, 850, 5, 6, 0xff, 2, 0},
  124. {2, 1050, 5, 7, 0xff, 2, 0},
  125. {2, 1250, 4, 6, 0xff, 2, 0},
  126. {2, 1350, 5, 7, 0xff, 2, 0},
  127. {2, 1666, 5, 8, 0xff, 2, 0},
  128. {1, 1250, 4, 6, 0xff, 2, 0},
  129. {1, 1335, 4, 7, 0xff, 2, 0},
  130. {1, 1666, 4, 8, 0xff, 2, 0},
  131. {}
  132. };
  133. /*
  134. * The two slots have slightly different timing. The center values are good
  135. * for both slots. We use identical speed tables for them. In future use, if
  136. * DIMMs have fewer center values that require two separated tables, copy the
  137. * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
  138. */
  139. static const struct board_specific_parameters *udimms[] = {
  140. udimm0,
  141. udimm0,
  142. };
  143. static const struct board_specific_parameters rdimm0[] = {
  144. /*
  145. * memory controller 0
  146. * num| hi| clk| wrlvl | cpo |wrdata|2T
  147. * ranks| mhz|adjst| start | |delay |
  148. */
  149. {4, 850, 4, 6, 0xff, 2, 0},
  150. {4, 950, 5, 7, 0xff, 2, 0},
  151. {4, 1050, 5, 8, 0xff, 2, 0},
  152. {4, 1250, 5, 10, 0xff, 2, 0},
  153. {4, 1350, 5, 11, 0xff, 2, 0},
  154. {4, 1666, 5, 12, 0xff, 2, 0},
  155. {2, 850, 4, 6, 0xff, 2, 0},
  156. {2, 1050, 4, 7, 0xff, 2, 0},
  157. {2, 1666, 4, 8, 0xff, 2, 0},
  158. {1, 850, 4, 5, 0xff, 2, 0},
  159. {1, 950, 4, 7, 0xff, 2, 0},
  160. {1, 1666, 4, 8, 0xff, 2, 0},
  161. {}
  162. };
  163. /*
  164. * The two slots have slightly different timing. See comments above.
  165. */
  166. static const struct board_specific_parameters *rdimms[] = {
  167. rdimm0,
  168. rdimm0,
  169. };
  170. void fsl_ddr_board_options(memctl_options_t *popts,
  171. dimm_params_t *pdimm,
  172. unsigned int ctrl_num)
  173. {
  174. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  175. ulong ddr_freq;
  176. if (ctrl_num > 1) {
  177. printf("Wrong parameter for controller number %d", ctrl_num);
  178. return;
  179. }
  180. if (!pdimm->n_ranks)
  181. return;
  182. if (popts->registered_dimm_en)
  183. pbsp = rdimms[ctrl_num];
  184. else
  185. pbsp = udimms[ctrl_num];
  186. /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  187. * freqency and n_banks specified in board_specific_parameters table.
  188. */
  189. ddr_freq = get_ddr_freq(0) / 1000000;
  190. while (pbsp->datarate_mhz_high) {
  191. if (pbsp->n_ranks == pdimm->n_ranks) {
  192. if (ddr_freq <= pbsp->datarate_mhz_high) {
  193. popts->cpo_override = pbsp->cpo;
  194. popts->write_data_delay =
  195. pbsp->write_data_delay;
  196. popts->clk_adjust = pbsp->clk_adjust;
  197. popts->wrlvl_start = pbsp->wrlvl_start;
  198. popts->twot_en = pbsp->force_2t;
  199. goto found;
  200. }
  201. pbsp_highest = pbsp;
  202. }
  203. pbsp++;
  204. }
  205. if (pbsp_highest) {
  206. printf("Error: board specific timing not found "
  207. "for data rate %lu MT/s!\n"
  208. "Trying to use the highest speed (%u) parameters\n",
  209. ddr_freq, pbsp_highest->datarate_mhz_high);
  210. popts->cpo_override = pbsp_highest->cpo;
  211. popts->write_data_delay = pbsp_highest->write_data_delay;
  212. popts->clk_adjust = pbsp_highest->clk_adjust;
  213. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  214. popts->twot_en = pbsp_highest->force_2t;
  215. } else {
  216. panic("DIMM is not supported by this board");
  217. }
  218. found:
  219. /*
  220. * Factors to consider for half-strength driver enable:
  221. * - number of DIMMs installed
  222. */
  223. popts->half_strength_driver_enable = 0;
  224. /*
  225. * Write leveling override
  226. */
  227. popts->wrlvl_override = 1;
  228. popts->wrlvl_sample = 0xf;
  229. /*
  230. * Rtt and Rtt_WR override
  231. */
  232. popts->rtt_override = 0;
  233. /* Enable ZQ calibration */
  234. popts->zq_en = 1;
  235. /* DHC_EN =1, ODT = 60 Ohm */
  236. popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
  237. }
  238. int dram_init(void)
  239. {
  240. phys_size_t dram_size;
  241. puts("Initializing....");
  242. if (fsl_use_spd()) {
  243. puts("using SPD\n");
  244. dram_size = fsl_ddr_sdram();
  245. } else {
  246. puts("using fixed parameters\n");
  247. dram_size = fixed_sdram();
  248. }
  249. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  250. dram_size *= 0x100000;
  251. debug(" DDR: ");
  252. gd->ram_size = dram_size;
  253. return 0;
  254. }