corenet_ds.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <fdt_support.h>
  9. #include <image.h>
  10. #include <init.h>
  11. #include <netdev.h>
  12. #include <linux/compiler.h>
  13. #include <asm/mmu.h>
  14. #include <asm/processor.h>
  15. #include <asm/cache.h>
  16. #include <asm/immap_85xx.h>
  17. #include <asm/fsl_law.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <asm/fsl_liodn.h>
  20. #include <fm_eth.h>
  21. #include "../common/ngpixis.h"
  22. #include "corenet_ds.h"
  23. DECLARE_GLOBAL_DATA_PTR;
  24. int checkboard (void)
  25. {
  26. u8 sw;
  27. struct cpu_type *cpu = gd->arch.cpu;
  28. #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
  29. defined(CONFIG_TARGET_P5040DS)
  30. unsigned int i;
  31. #endif
  32. static const char * const freq[] = {"100", "125", "156.25", "212.5" };
  33. printf("Board: %sDS, ", cpu->name);
  34. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  35. in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
  36. sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
  37. sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
  38. if (sw < 0x8)
  39. printf("vBank: %d\n", sw);
  40. else if (sw == 0x8)
  41. puts("Promjet\n");
  42. else if (sw == 0x9)
  43. puts("NAND\n");
  44. else
  45. printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
  46. /* Display the actual SERDES reference clocks as configured by the
  47. * dip switches on the board. Note that the SWx registers could
  48. * technically be set to force the reference clocks to match the
  49. * values that the SERDES expects (or vice versa). For now, however,
  50. * we just display both values and hope the user notices when they
  51. * don't match.
  52. */
  53. puts("SERDES Reference Clocks: ");
  54. #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
  55. defined(CONFIG_TARGET_P5040DS)
  56. sw = in_8(&PIXIS_SW(5));
  57. for (i = 0; i < 3; i++) {
  58. unsigned int clock = (sw >> (6 - (2 * i))) & 3;
  59. printf("Bank%u=%sMhz ", i+1, freq[clock]);
  60. }
  61. #ifdef CONFIG_TARGET_P5040DS
  62. /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
  63. sw = in_8(&PIXIS_SW(9));
  64. printf("Bank4=%sMhz ", freq[sw & 3]);
  65. #endif
  66. puts("\n");
  67. #else
  68. sw = in_8(&PIXIS_SW(3));
  69. /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */
  70. /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */
  71. /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */
  72. printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]);
  73. printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]);
  74. printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]);
  75. #endif
  76. return 0;
  77. }
  78. int board_early_init_f(void)
  79. {
  80. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  81. /*
  82. * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
  83. * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
  84. * the noise introduced by these unterminated and unused clock pairs.
  85. */
  86. setbits_be32(&gur->ddrclkdr, 0x001B001B);
  87. return 0;
  88. }
  89. int board_early_init_r(void)
  90. {
  91. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  92. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  93. /*
  94. * Remap Boot flash + PROMJET region to caching-inhibited
  95. * so that flash can be erased properly.
  96. */
  97. /* Flush d-cache and invalidate i-cache of any FLASH data */
  98. flush_dcache();
  99. invalidate_icache();
  100. if (flash_esel == -1) {
  101. /* very unlikely unless something is messed up */
  102. puts("Error: Could not find TLB for FLASH BASE\n");
  103. flash_esel = 2; /* give our best effort to continue */
  104. } else {
  105. /* invalidate existing TLB entry for flash + promjet */
  106. disable_tlb(flash_esel);
  107. }
  108. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  109. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
  110. 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
  111. return 0;
  112. }
  113. #define NUM_SRDS_BANKS 3
  114. int misc_init_r(void)
  115. {
  116. serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  117. u32 actual[NUM_SRDS_BANKS];
  118. unsigned int i;
  119. u8 sw;
  120. #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
  121. defined(CONFIG_TARGET_P5040DS)
  122. sw = in_8(&PIXIS_SW(5));
  123. for (i = 0; i < 3; i++) {
  124. unsigned int clock = (sw >> (6 - (2 * i))) & 3;
  125. switch (clock) {
  126. case 0:
  127. actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
  128. break;
  129. case 1:
  130. actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
  131. break;
  132. case 2:
  133. actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
  134. break;
  135. default:
  136. printf("Warning: SDREFCLK%u switch setting of '11' is "
  137. "unsupported\n", i + 1);
  138. break;
  139. }
  140. }
  141. #else
  142. /* Warn if the expected SERDES reference clocks don't match the
  143. * actual reference clocks. This needs to be done after calling
  144. * p4080_erratum_serdes8(), since that function may modify the clocks.
  145. */
  146. sw = in_8(&PIXIS_SW(3));
  147. actual[0] = (sw & 0x40) ?
  148. SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
  149. actual[1] = (sw & 0x20) ?
  150. SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
  151. actual[2] = (sw & 0x10) ?
  152. SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
  153. #endif
  154. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  155. u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
  156. if (expected != actual[i]) {
  157. printf("Warning: SERDES bank %u expects reference clock"
  158. " %sMHz, but actual is %sMHz\n", i + 1,
  159. serdes_clock_to_string(expected),
  160. serdes_clock_to_string(actual[i]));
  161. }
  162. }
  163. return 0;
  164. }
  165. int ft_board_setup(void *blob, struct bd_info *bd)
  166. {
  167. phys_addr_t base;
  168. phys_size_t size;
  169. ft_cpu_setup(blob, bd);
  170. base = env_get_bootm_low();
  171. size = env_get_bootm_size();
  172. fdt_fixup_memory(blob, (u64)base, (u64)size);
  173. #ifdef CONFIG_PCI
  174. pci_of_setup(blob, bd);
  175. #endif
  176. fdt_fixup_liodn(blob);
  177. fsl_fdt_fixup_dr_usb(blob, bd);
  178. #ifdef CONFIG_SYS_DPAA_FMAN
  179. #ifndef CONFIG_DM_ETH
  180. fdt_fixup_fman_ethernet(blob);
  181. #endif
  182. fdt_fixup_board_enet(blob);
  183. #endif
  184. return 0;
  185. }