dns325.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011
  4. * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
  5. *
  6. * Based on Kirkwood support:
  7. * (C) Copyright 2009
  8. * Marvell Semiconductor <www.marvell.com>
  9. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  10. */
  11. #include <common.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <miiphy.h>
  15. #include <net.h>
  16. #include <netdev.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/soc.h>
  19. #include <asm/arch/mpp.h>
  20. #include <asm/arch/gpio.h>
  21. #include "dns325.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. int board_early_init_f(void)
  24. {
  25. /* Gpio configuration */
  26. mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
  27. DNS325_OE_LOW, DNS325_OE_HIGH);
  28. /* Multi-Purpose Pins Functionality configuration */
  29. static const u32 kwmpp_config[] = {
  30. MPP0_NF_IO2,
  31. MPP1_NF_IO3,
  32. MPP2_NF_IO4,
  33. MPP3_NF_IO5,
  34. MPP4_NF_IO6,
  35. MPP5_NF_IO7,
  36. MPP6_SYSRST_OUTn,
  37. MPP7_GPO,
  38. MPP8_TW_SDA,
  39. MPP9_TW_SCK,
  40. MPP10_UART0_TXD,
  41. MPP11_UART0_RXD,
  42. MPP12_SD_CLK,
  43. MPP13_SD_CMD,
  44. MPP14_SD_D0,
  45. MPP15_SD_D1,
  46. MPP16_SD_D2,
  47. MPP17_SD_D3,
  48. MPP18_NF_IO0,
  49. MPP19_NF_IO1,
  50. MPP20_SATA1_ACTn, /* sata1(left) status led */
  51. MPP21_SATA0_ACTn, /* sata0(right) status led */
  52. MPP22_GPIO,
  53. MPP23_GPIO,
  54. MPP24_GPIO, /* power off out */
  55. MPP25_GPIO,
  56. MPP26_GPIO, /* power led */
  57. MPP27_GPIO, /* sata0(right) error led */
  58. MPP28_GPIO, /* sata1(left) error led */
  59. MPP29_GPIO, /* usb error led */
  60. MPP30_GPIO,
  61. MPP31_GPIO,
  62. MPP32_GPIO,
  63. MPP33_GPIO,
  64. MPP34_GPIO, /* power key */
  65. MPP35_GPIO,
  66. MPP36_GPIO,
  67. MPP37_GPIO,
  68. MPP38_GPIO,
  69. MPP39_GPIO, /* enable sata 0 */
  70. MPP40_GPIO, /* enable sata 1 */
  71. MPP41_GPIO, /* hdd0 present */
  72. MPP42_GPIO, /* hdd1 present */
  73. MPP43_GPIO, /* usb status led */
  74. MPP44_GPIO, /* fan status */
  75. MPP45_GPIO, /* fan high speed */
  76. MPP46_GPIO, /* fan low speed */
  77. MPP47_GPIO, /* usb umount */
  78. MPP48_GPIO, /* factory reset */
  79. MPP49_GPIO, /* thermal sensor */
  80. 0
  81. };
  82. kirkwood_mpp_conf(kwmpp_config, NULL);
  83. kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
  84. kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
  85. return 0;
  86. }
  87. int board_init(void)
  88. {
  89. /* Boot parameters address */
  90. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  91. return 0;
  92. }
  93. #ifdef CONFIG_RESET_PHY_R
  94. /* Configure and initialize PHY */
  95. void reset_phy(void)
  96. {
  97. u16 reg;
  98. u16 devadr;
  99. char *name = "egiga0";
  100. if (miiphy_set_current_dev(name))
  101. return;
  102. /* command to read PHY dev address */
  103. if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
  104. printf("Err..(%s) could not read PHY dev address\n", __func__);
  105. return;
  106. }
  107. /*
  108. * Enable RGMII delay on Tx and Rx for CPU port
  109. * Ref: sec 4.7.2 of chip datasheet
  110. */
  111. miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
  112. miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
  113. reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
  114. miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
  115. miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
  116. /* reset the phy */
  117. miiphy_reset(name, devadr);
  118. debug("88E1116 Initialized on %s\n", name);
  119. }
  120. #endif /* CONFIG_RESET_PHY_R */