edb93xx.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board initialization for EP93xx
  4. *
  5. * Copyright (C) 2013
  6. * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
  7. *
  8. * Copyright (C) 2009
  9. * Matthias Kaehlcke <matthias <at> kaehlcke.net>
  10. *
  11. * (C) Copyright 2002 2003
  12. * Network Audio Technologies, Inc. <www.netaudiotech.com>
  13. * Adam Bezanson <bezanson <at> netaudiotech.com>
  14. */
  15. #include <config.h>
  16. #include <common.h>
  17. #include <cpu_func.h>
  18. #include <init.h>
  19. #include <irq_func.h>
  20. #include <net.h>
  21. #include <netdev.h>
  22. #include <status_led.h>
  23. #include <asm/io.h>
  24. #include <asm/mach-types.h>
  25. #include <asm/arch/ep93xx.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. /*
  28. * usb_div: 4, nbyp2: 1, pll2_en: 1
  29. * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
  30. * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
  31. */
  32. #define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
  33. 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
  34. 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
  35. 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
  36. SYSCON_CLKSET2_PLL2_EN | \
  37. SYSCON_CLKSET2_NBYP2 | \
  38. 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
  39. #define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
  40. SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
  41. 1 << SMC_BCR_MW_SHIFT)
  42. /* delay execution before timers are initialized */
  43. static inline void early_udelay(uint32_t usecs)
  44. {
  45. /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
  46. register uint32_t loops = (usecs * 1000) / 20;
  47. __asm__ volatile ("1:\n"
  48. "subs %0, %1, #1\n"
  49. "bne 1b" : "=r" (loops) : "0" (loops));
  50. }
  51. #ifndef CONFIG_EP93XX_NO_FLASH_CFG
  52. static void flash_cfg(void)
  53. {
  54. struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
  55. writel(SMC_BCR6_VALUE, &smc->bcr6);
  56. }
  57. #else
  58. #define flash_cfg()
  59. #endif
  60. int board_init(void)
  61. {
  62. /*
  63. * Setup PLL2, PPL1 has been set during lowlevel init
  64. */
  65. struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  66. writel(CLKSET2_VAL, &syscon->clkset2);
  67. /*
  68. * the user's guide recommends to wait at least 1 ms for PLL2 to
  69. * stabilize
  70. */
  71. early_udelay(1000);
  72. /* Go to Async mode */
  73. __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
  74. __asm__ volatile ("orr r0, r0, #0xc0000000");
  75. __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
  76. icache_enable();
  77. #ifdef USE_920T_MMU
  78. dcache_enable();
  79. #endif
  80. /* Machine number, as defined in linux/arch/arm/tools/mach-types */
  81. gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
  82. /* adress of boot parameters */
  83. gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  84. /* We have a console */
  85. gd->have_console = 1;
  86. enable_interrupts();
  87. flash_cfg();
  88. green_led_on();
  89. red_led_off();
  90. return 0;
  91. }
  92. int board_early_init_f(void)
  93. {
  94. /*
  95. * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
  96. * 14.7456/2 MHz
  97. */
  98. struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  99. writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
  100. return 0;
  101. }
  102. int board_eth_init(struct bd_info *bd)
  103. {
  104. return ep93xx_eth_initialize(0, MAC_BASE);
  105. }
  106. static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt,
  107. unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS])
  108. {
  109. if (dram_bank_cnt == 1) {
  110. dram_bank_base[0] = PHYS_SDRAM_1;
  111. } else {
  112. /* Table lookup for holes in address space. Maximum memory
  113. * for the single SDCS may be up to 256Mb. We start scanning
  114. * banks from 1Mb, so it could be up to 128 banks theoretically.
  115. * We need at maximum 7 bits for the loockup, 8 slots is
  116. * enough for the worst case.
  117. */
  118. unsigned tbl[8];
  119. unsigned i = dram_bank_cnt / 2;
  120. unsigned j = 0x00100000; /* 1 Mb */
  121. unsigned *ptbl = tbl;
  122. do {
  123. while (!(dram_addr_mask & j)) {
  124. j <<= 1;
  125. }
  126. *ptbl++ = j;
  127. j <<= 1;
  128. i >>= 1;
  129. } while (i != 0);
  130. for (i = dram_bank_cnt, j = 0;
  131. (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
  132. unsigned addr = PHYS_SDRAM_1;
  133. unsigned k;
  134. unsigned bit;
  135. for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
  136. if (bit & j)
  137. addr |= tbl[k];
  138. }
  139. dram_bank_base[j] = addr;
  140. }
  141. }
  142. }
  143. /* called in board_init_f (before relocation) */
  144. static unsigned dram_init_banksize_int(int print)
  145. {
  146. /*
  147. * Collect information of banks that has been filled during lowlevel
  148. * initialization
  149. */
  150. unsigned i;
  151. unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
  152. unsigned dram_total = 0;
  153. unsigned dram_bank_size = *(unsigned *)
  154. (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE);
  155. unsigned dram_addr_mask = *(unsigned *)
  156. (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK);
  157. unsigned dram_bank_cnt = *(unsigned *)
  158. (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT);
  159. dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
  160. for (i = 0; i < dram_bank_cnt; i++) {
  161. gd->bd->bi_dram[i].start = dram_bank_base[i];
  162. gd->bd->bi_dram[i].size = dram_bank_size;
  163. dram_total += dram_bank_size;
  164. }
  165. for (; i < CONFIG_NR_DRAM_BANKS; i++) {
  166. gd->bd->bi_dram[i].start = 0;
  167. gd->bd->bi_dram[i].size = 0;
  168. }
  169. if (print) {
  170. printf("DRAM mask: %08x\n", dram_addr_mask);
  171. printf("DRAM total %u banks:\n", dram_bank_cnt);
  172. printf("bank base-address size\n");
  173. if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
  174. printf("WARNING! UBoot was configured for %u banks,\n"
  175. "but %u has been found. "
  176. "Supressing extra memory banks\n",
  177. CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
  178. dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
  179. }
  180. for (i = 0; i < dram_bank_cnt; i++) {
  181. printf(" %u %08x %08x\n",
  182. i, dram_bank_base[i], dram_bank_size);
  183. }
  184. printf(" ------------------------------------------\n"
  185. "Total %9d\n\n",
  186. dram_total);
  187. }
  188. return dram_total;
  189. }
  190. int dram_init_banksize(void)
  191. {
  192. dram_init_banksize_int(0);
  193. return 0;
  194. }
  195. /* called in board_init_f (before relocation) */
  196. int dram_init(void)
  197. {
  198. struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  199. unsigned sec_id = readl(SECURITY_EXTENSIONID);
  200. unsigned chip_id = readl(&syscon->chipid);
  201. printf("CPU: Cirrus Logic ");
  202. switch (sec_id & 0x000001FE) {
  203. case 0x00000008:
  204. printf("EP9301");
  205. break;
  206. case 0x00000004:
  207. printf("EP9307");
  208. break;
  209. case 0x00000002:
  210. printf("EP931x");
  211. break;
  212. case 0x00000000:
  213. printf("EP9315");
  214. break;
  215. default:
  216. printf("<unknown>");
  217. break;
  218. }
  219. printf(" - Rev. ");
  220. switch (chip_id & 0xF0000000) {
  221. case 0x00000000:
  222. printf("A");
  223. break;
  224. case 0x10000000:
  225. printf("B");
  226. break;
  227. case 0x20000000:
  228. printf("C");
  229. break;
  230. case 0x30000000:
  231. printf("D0");
  232. break;
  233. case 0x40000000:
  234. printf("D1");
  235. break;
  236. case 0x50000000:
  237. printf("E0");
  238. break;
  239. case 0x60000000:
  240. printf("E1");
  241. break;
  242. case 0x70000000:
  243. printf("E2");
  244. break;
  245. default:
  246. printf("?");
  247. break;
  248. }
  249. printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
  250. gd->ram_size = dram_init_banksize_int(1);
  251. return 0;
  252. }