mx53cx9020.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
  4. * Patrick Bruenn <p.bruenn@beckhoff.com>
  5. *
  6. * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c
  7. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <init.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/iomux-mx53.h>
  15. #include <asm/mach-imx/mx5_video.h>
  16. #include <ACEX1K.h>
  17. #include <asm/gpio.h>
  18. #include <linux/delay.h>
  19. enum LED_GPIOS {
  20. GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
  21. GPIO_SD2_CD = IMX_GPIO_NR(1, 4),
  22. GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),
  23. GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),
  24. GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),
  25. GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),
  26. GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),
  27. GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),
  28. GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),
  29. GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),
  30. GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),
  31. GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),
  32. GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),
  33. GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),
  34. GPIO_C3_DONE = IMX_GPIO_NR(6, 9),
  35. };
  36. #define CCAT_BASE_ADDR ((void *)0xf0000000)
  37. #define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32))
  38. #define CCAT_SIZE 1191788
  39. #define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12)
  40. static const char CCAT_SIGNATURE[] = "CCAT";
  41. static const u32 CCAT_MODE_CONFIG = 0x0024DC81;
  42. static const u32 CCAT_MODE_RUN = 0x0033DC8F;
  43. DECLARE_GLOBAL_DATA_PTR;
  44. u32 get_board_rev(void)
  45. {
  46. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  47. struct fuse_bank *bank = &iim->bank[0];
  48. struct fuse_bank0_regs *fuse =
  49. (struct fuse_bank0_regs *)bank->fuse_regs;
  50. int rev = readl(&fuse->gp[6]);
  51. return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  52. }
  53. /*
  54. * Set CCAT mode
  55. * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN
  56. */
  57. void weim_cs0_settings(u32 mode)
  58. {
  59. struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
  60. writel(0x0, &weim_regs->cs0gcr1);
  61. writel(mode, &weim_regs->cs0gcr1);
  62. writel(0x00001002, &weim_regs->cs0gcr2);
  63. writel(0x04000000, &weim_regs->cs0rcr1);
  64. writel(0x00000000, &weim_regs->cs0rcr2);
  65. writel(0x04000000, &weim_regs->cs0wcr1);
  66. writel(0x00000000, &weim_regs->cs0wcr2);
  67. }
  68. static void setup_gpio_eim(void)
  69. {
  70. gpio_request(GPIO_C3_STATUS, "GPIO_C3_STATUS");
  71. gpio_request(GPIO_C3_DONE, "GPIO_C3_DONE");
  72. gpio_request(GPIO_C3_CONFIG, "GPIO_C3_CONFIG");
  73. gpio_direction_input(GPIO_C3_STATUS);
  74. gpio_direction_input(GPIO_C3_DONE);
  75. gpio_direction_output(GPIO_C3_CONFIG, 1);
  76. weim_cs0_settings(CCAT_MODE_RUN);
  77. }
  78. static void setup_gpio_sups(void)
  79. {
  80. gpio_request(GPIO_SUPS_INT, "GPIO_SUPS_INT");
  81. gpio_direction_input(GPIO_SUPS_INT);
  82. static const int BLINK_INTERVALL = 50000;
  83. int status = 1;
  84. while (gpio_get_value(GPIO_SUPS_INT)) {
  85. /* signal "CX SUPS power fail" */
  86. gpio_set_value(GPIO_LED_PWR_R,
  87. (++status / BLINK_INTERVALL) % 2);
  88. }
  89. /* signal "CX power up" */
  90. gpio_set_value(GPIO_LED_PWR_R, 1);
  91. }
  92. static void setup_gpio_leds(void)
  93. {
  94. gpio_request(GPIO_LED_SD2_R, "GPIO_LED_SD2_R");
  95. gpio_request(GPIO_LED_SD2_B, "GPIO_LED_SD2_B");
  96. gpio_request(GPIO_LED_SD2_G, "GPIO_LED_SD2_G");
  97. gpio_request(GPIO_LED_SD1_R, "GPIO_LED_SD1_R");
  98. gpio_request(GPIO_LED_SD1_B, "GPIO_LED_SD1_B");
  99. gpio_request(GPIO_LED_SD1_G, "GPIO_LED_SD1_G");
  100. gpio_request(GPIO_LED_PWR_R, "GPIO_LED_PWR_R");
  101. gpio_request(GPIO_LED_PWR_B, "GPIO_LED_PWR_B");
  102. gpio_request(GPIO_LED_PWR_G, "GPIO_LED_PWR_G");
  103. gpio_direction_output(GPIO_LED_SD2_R, 0);
  104. gpio_direction_output(GPIO_LED_SD2_B, 0);
  105. gpio_direction_output(GPIO_LED_SD2_G, 0);
  106. gpio_direction_output(GPIO_LED_SD1_R, 0);
  107. gpio_direction_output(GPIO_LED_SD1_B, 0);
  108. gpio_direction_output(GPIO_LED_SD1_G, 0);
  109. gpio_direction_output(GPIO_LED_PWR_R, 0);
  110. gpio_direction_output(GPIO_LED_PWR_B, 0);
  111. gpio_direction_output(GPIO_LED_PWR_G, 0);
  112. }
  113. static int power_init(void)
  114. {
  115. /* nothing to do on CX9020 */
  116. return 0;
  117. }
  118. static void clock_1GHz(void)
  119. {
  120. int ret;
  121. u32 ref_clk = MXC_HCLK;
  122. /*
  123. * After increasing voltage to 1.25V, we can switch
  124. * CPU clock to 1GHz and DDR to 400MHz safely
  125. */
  126. ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
  127. if (ret)
  128. printf("CPU: Switch CPU clock to 1GHZ failed\n");
  129. ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
  130. ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
  131. if (ret)
  132. printf("CPU: Switch DDR clock to 400MHz failed\n");
  133. }
  134. int board_early_init_f(void)
  135. {
  136. return 0;
  137. }
  138. int board_init(void)
  139. {
  140. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  141. mxc_set_sata_internal_clock();
  142. setup_gpio_leds();
  143. setup_gpio_sups();
  144. setup_gpio_eim();
  145. setup_iomux_lcd();
  146. return 0;
  147. }
  148. int checkboard(void)
  149. {
  150. puts("Board: Beckhoff CX9020\n");
  151. return 0;
  152. }
  153. static int ccat_config_fn(int assert_config, int flush, int cookie)
  154. {
  155. /* prepare FPGA for programming */
  156. weim_cs0_settings(CCAT_MODE_CONFIG);
  157. gpio_set_value(GPIO_C3_CONFIG, 0);
  158. udelay(1);
  159. gpio_set_value(GPIO_C3_CONFIG, 1);
  160. udelay(230);
  161. return FPGA_SUCCESS;
  162. }
  163. static int ccat_status_fn(int cookie)
  164. {
  165. return FPGA_FAIL;
  166. }
  167. static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie)
  168. {
  169. const uint8_t *const buffer = buf;
  170. /* program CCAT */
  171. int i;
  172. for (i = 0; i < buf_len; ++i)
  173. writeb(buffer[i], CCAT_BASE_ADDR);
  174. writeb(0xff, CCAT_BASE_ADDR);
  175. writeb(0xff, CCAT_BASE_ADDR);
  176. return FPGA_SUCCESS;
  177. }
  178. static int ccat_done_fn(int cookie)
  179. {
  180. /* programming complete? */
  181. return gpio_get_value(GPIO_C3_DONE);
  182. }
  183. static int ccat_post_fn(int cookie)
  184. {
  185. /* switch to FPGA run mode */
  186. weim_cs0_settings(CCAT_MODE_RUN);
  187. invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR);
  188. if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) {
  189. printf("Verifing CCAT firmware failed, signature not found\n");
  190. return FPGA_FAIL;
  191. }
  192. /* signal "CX booting OS" */
  193. gpio_set_value(GPIO_LED_PWR_R, 1);
  194. gpio_set_value(GPIO_LED_PWR_G, 1);
  195. gpio_set_value(GPIO_LED_PWR_B, 0);
  196. return FPGA_SUCCESS;
  197. }
  198. static Altera_CYC2_Passive_Serial_fns ccat_fns = {
  199. .config = ccat_config_fn,
  200. .status = ccat_status_fn,
  201. .done = ccat_done_fn,
  202. .write = ccat_write_fn,
  203. .abort = ccat_post_fn,
  204. .post = ccat_post_fn,
  205. };
  206. static Altera_desc ccat_fpga = {
  207. .family = Altera_CYC2,
  208. .iface = passive_serial,
  209. .size = CCAT_SIZE,
  210. .iface_fns = &ccat_fns,
  211. .base = CCAT_BASE_ADDR,
  212. };
  213. int board_late_init(void)
  214. {
  215. if (!power_init())
  216. clock_1GHz();
  217. fpga_init();
  218. fpga_add(fpga_altera, &ccat_fpga);
  219. return 0;
  220. }