spl.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. #include <common.h>
  3. #include <cpu_func.h>
  4. #include <hang.h>
  5. #include <init.h>
  6. #include <log.h>
  7. #include <spl.h>
  8. #include <asm/io.h>
  9. #include <asm/mach-imx/iomux-v3.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/imx8mm_pins.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/mach-imx/boot_mode.h>
  14. #include <asm/arch/ddr.h>
  15. #include <dm/uclass.h>
  16. #include <dm/device.h>
  17. #include <dm/uclass-internal.h>
  18. #include <dm/device-internal.h>
  19. #include <power/pmic.h>
  20. #include <power/bd71837.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. int spl_board_boot_device(enum boot_device boot_dev_spl)
  23. {
  24. switch (boot_dev_spl) {
  25. case SD2_BOOT:
  26. case MMC2_BOOT:
  27. return BOOT_DEVICE_MMC1;
  28. case SD3_BOOT:
  29. case MMC3_BOOT:
  30. return BOOT_DEVICE_MMC2;
  31. default:
  32. return BOOT_DEVICE_NONE;
  33. }
  34. }
  35. static void spl_dram_init(void)
  36. {
  37. ddr_init(&dram_timing);
  38. }
  39. void spl_board_init(void)
  40. {
  41. debug("Normal Boot\n");
  42. }
  43. #ifdef CONFIG_SPL_LOAD_FIT
  44. int board_fit_config_name_match(const char *name)
  45. {
  46. /* Just empty function now - can't decide what to choose */
  47. debug("%s: %s\n", __func__, name);
  48. return 0;
  49. }
  50. #endif
  51. #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  52. #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  53. static iomux_v3_cfg_t const uart_pads[] = {
  54. IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  55. IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  56. };
  57. static iomux_v3_cfg_t const wdog_pads[] = {
  58. IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  59. };
  60. int board_early_init_f(void)
  61. {
  62. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  63. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  64. set_wdog_reset(wdog);
  65. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  66. return 0;
  67. }
  68. static int power_init_board(void)
  69. {
  70. struct udevice *dev;
  71. int ret;
  72. ret = pmic_get("pmic@4b", &dev);
  73. if (ret == -ENODEV) {
  74. puts("No pmic\n");
  75. return 0;
  76. }
  77. if (ret != 0)
  78. return ret;
  79. /* decrease RESET key long push time from the default 10s to 10ms */
  80. pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
  81. /* unlock the PMIC regs */
  82. pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
  83. /* increase VDD_SOC to typical value 0.85v before first DRAM access */
  84. pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
  85. /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
  86. pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
  87. /* lock the PMIC regs */
  88. pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
  89. return 0;
  90. }
  91. void board_init_f(ulong dummy)
  92. {
  93. struct udevice *dev;
  94. int ret;
  95. arch_cpu_init();
  96. init_uart_clk(1);
  97. board_early_init_f();
  98. timer_init();
  99. preloader_console_init();
  100. /* Clear the BSS. */
  101. memset(__bss_start, 0, __bss_end - __bss_start);
  102. ret = spl_early_init();
  103. if (ret) {
  104. debug("spl_early_init() failed: %d\n", ret);
  105. hang();
  106. }
  107. ret = uclass_get_device_by_name(UCLASS_CLK,
  108. "clock-controller@30380000",
  109. &dev);
  110. if (ret < 0) {
  111. printf("Failed to find clock node. Check device tree\n");
  112. hang();
  113. }
  114. enable_tzc380();
  115. power_init_board();
  116. /* DDR initialization */
  117. spl_dram_init();
  118. board_init_r(NULL, 0);
  119. }