sam9x60ek.c 3.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
  4. *
  5. * Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/at91sam9_smc.h>
  11. #include <asm/arch/at91_common.h>
  12. #include <asm/arch/at91_rstc.h>
  13. #include <asm/arch/at91_sfr.h>
  14. #include <asm/arch/clk.h>
  15. #include <asm/arch/gpio.h>
  16. #include <debug_uart.h>
  17. #include <asm/mach-types.h>
  18. extern void at91_pda_detect(void);
  19. DECLARE_GLOBAL_DATA_PTR;
  20. void at91_prepare_cpu_var(void);
  21. #ifdef CONFIG_CMD_NAND
  22. static void sam9x60ek_nand_hw_init(void)
  23. {
  24. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  25. struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
  26. unsigned int csa;
  27. at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
  28. at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
  29. at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */
  30. at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */
  31. /* Enable NandFlash */
  32. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  33. /* Configure RDY/BSY */
  34. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  35. at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
  36. at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
  37. at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
  38. at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
  39. at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
  40. at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
  41. at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
  42. at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
  43. at91_periph_clk_enable(ATMEL_ID_PIOD);
  44. /* Enable CS3 */
  45. csa = readl(&sfr->ebicsa);
  46. csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16;
  47. /* Configure IO drive */
  48. csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60;
  49. writel(csa, &sfr->ebicsa);
  50. /* Configure SMC CS3 for NAND/SmartMedia */
  51. writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup);
  52. writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) |
  53. AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20),
  54. &smc->cs[3].pulse);
  55. writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
  56. &smc->cs[3].cycle);
  57. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  58. #ifdef CONFIG_SYS_NAND_DBW_16
  59. AT91_SMC_MODE_DBW_16 |
  60. #else /* CONFIG_SYS_NAND_DBW_8 */
  61. AT91_SMC_MODE_DBW_8 |
  62. #endif
  63. AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15),
  64. &smc->cs[3].mode);
  65. }
  66. #endif
  67. #ifdef CONFIG_BOARD_LATE_INIT
  68. int board_late_init(void)
  69. {
  70. at91_prepare_cpu_var();
  71. at91_pda_detect();
  72. return 0;
  73. }
  74. #endif
  75. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  76. void board_debug_uart_init(void)
  77. {
  78. at91_seriald_hw_init();
  79. }
  80. #endif
  81. #ifdef CONFIG_BOARD_EARLY_INIT_F
  82. int board_early_init_f(void)
  83. {
  84. #ifdef CONFIG_DEBUG_UART
  85. debug_uart_init();
  86. #endif
  87. return 0;
  88. }
  89. #endif
  90. #define MAC24AA_MAC_OFFSET 0xfa
  91. #ifdef CONFIG_MISC_INIT_R
  92. int misc_init_r(void)
  93. {
  94. #ifdef CONFIG_I2C_EEPROM
  95. at91_set_ethaddr(MAC24AA_MAC_OFFSET);
  96. #endif
  97. return 0;
  98. }
  99. #endif
  100. int board_init(void)
  101. {
  102. /* address of boot parameters */
  103. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  104. #ifdef CONFIG_CMD_NAND
  105. sam9x60ek_nand_hw_init();
  106. #endif
  107. return 0;
  108. }
  109. int dram_init(void)
  110. {
  111. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  112. CONFIG_SYS_SDRAM_SIZE);
  113. return 0;
  114. }