armadillo-800eva.c 8.0 KB

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  1. /*
  2. * Copyright (C) 2012 Renesas Solutions Corp.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <cpu_func.h>
  24. #include <init.h>
  25. #include <malloc.h>
  26. #include <asm/processor.h>
  27. #include <asm/mach-types.h>
  28. #include <asm/io.h>
  29. #include <asm/arch/sys_proto.h>
  30. #include <asm/gpio.h>
  31. #include <asm/arch/rmobile.h>
  32. #define s_init_wait(cnt) \
  33. ({ \
  34. volatile u32 i = 0x10000 * cnt; \
  35. while (i > 0) \
  36. i--; \
  37. })
  38. #define USBCR1 0xE605810A
  39. void s_init(void)
  40. {
  41. struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE;
  42. struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE;
  43. struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE;
  44. struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE;
  45. struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE;
  46. struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE;
  47. /* Watchdog init */
  48. writew(0xA500, &rwdt0->rwtcsra0);
  49. writew(0xA500, &rwdt1->rwtcsra0);
  50. /* CPG */
  51. writel(0xFF800080, &cpg->rmstpcr4);
  52. writel(0xFF800080, &cpg->smstpcr4);
  53. /* USB clock */
  54. writel(0x00000080, &cpg->usbckcr);
  55. s_init_wait(1);
  56. /* USBCR1 */
  57. writew(0x0710, USBCR1);
  58. /* FRQCR */
  59. writel(0x00000000, &cpg->frqcrb);
  60. writel(0x62030533, &cpg->frqcra);
  61. writel(0x208A354E, &cpg->frqcrc);
  62. writel(0x80331050, &cpg->frqcrb);
  63. s_init_wait(1);
  64. writel(0x00000000, &cpg->frqcrd);
  65. s_init_wait(1);
  66. /* SUBClk */
  67. writel(0x0000010B, &cpg->subckcr);
  68. /* PLL */
  69. writel(0x00004004, &cpg->pllc01cr);
  70. s_init_wait(1);
  71. writel(0xa0000000, &cpg->pllc2cr);
  72. s_init_wait(2);
  73. /* BSC */
  74. writel(0x0000001B, &bsc->cmncr);
  75. writel(0x20000000, &dbsc->dbcmd);
  76. writel(0x10009C40, &dbsc->dbcmd);
  77. s_init_wait(1);
  78. writel(0x00000007, &dbsc->dbkind);
  79. writel(0x0E030A02, &dbsc->dbconf0);
  80. writel(0x00000001, &dbsc->dbphytype);
  81. writel(0x00000000, &dbsc->dbbl);
  82. writel(0x00000006, &dbsc->dbtr0);
  83. writel(0x00000005, &dbsc->dbtr1);
  84. writel(0x00000000, &dbsc->dbtr2);
  85. writel(0x00000006, &dbsc->dbtr3);
  86. writel(0x00080006, &dbsc->dbtr4);
  87. writel(0x00000015, &dbsc->dbtr5);
  88. writel(0x0000000f, &dbsc->dbtr6);
  89. writel(0x00000004, &dbsc->dbtr7);
  90. writel(0x00000018, &dbsc->dbtr8);
  91. writel(0x00000006, &dbsc->dbtr9);
  92. writel(0x00000006, &dbsc->dbtr10);
  93. writel(0x0000000F, &dbsc->dbtr11);
  94. writel(0x0000000D, &dbsc->dbtr12);
  95. writel(0x000000A0, &dbsc->dbtr13);
  96. writel(0x000A0003, &dbsc->dbtr14);
  97. writel(0x00000003, &dbsc->dbtr15);
  98. writel(0x40005005, &dbsc->dbtr16);
  99. writel(0x0C0C0000, &dbsc->dbtr17);
  100. writel(0x00000200, &dbsc->dbtr18);
  101. writel(0x00000040, &dbsc->dbtr19);
  102. writel(0x00000001, &dbsc->dbrnk0);
  103. writel(0x00000110, &dbsc->dbdficnt);
  104. writel(0x00000101, &ddrp->funcctrl);
  105. writel(0x00000001, &ddrp->dllctrl);
  106. writel(0x00000186, &ddrp->zqcalctrl);
  107. writel(0xB3440051, &ddrp->zqodtctrl);
  108. writel(0x94449443, &ddrp->rdctrl);
  109. writel(0x000000C0, &ddrp->rdtmg);
  110. writel(0x00000101, &ddrp->fifoinit);
  111. writel(0x02060506, &ddrp->outctrl);
  112. writel(0x00004646, &ddrp->dqcalofs1);
  113. writel(0x00004646, &ddrp->dqcalofs2);
  114. writel(0x800000aa, &ddrp->dqcalexp);
  115. writel(0x00000000, &ddrp->dllctrl);
  116. writel(0x00000000, DDRPNCNT);
  117. writel(0x0000000C, &dbsc->dbcmd);
  118. readl(&dbsc->dbwait);
  119. s_init_wait(1);
  120. writel(0x00000002, DDRPNCNT);
  121. writel(0x0000000C, &dbsc->dbcmd);
  122. readl(&dbsc->dbwait);
  123. s_init_wait(1);
  124. writel(0x00000187, &ddrp->zqcalctrl);
  125. writel(0x00009C40, &dbsc->dbcmd);
  126. readl(&dbsc->dbwait);
  127. s_init_wait(1);
  128. writel(0x00009C40, &dbsc->dbcmd);
  129. readl(&dbsc->dbwait);
  130. s_init_wait(1);
  131. writel(0x00000010, &dbsc->dbdficnt);
  132. writel(0x02060507, &ddrp->outctrl);
  133. writel(0x00009C40, &dbsc->dbcmd);
  134. readl(&dbsc->dbwait);
  135. s_init_wait(1);
  136. writel(0x21009C40, &dbsc->dbcmd);
  137. readl(&dbsc->dbwait);
  138. s_init_wait(1);
  139. writel(0x00009C40, &dbsc->dbcmd);
  140. readl(&dbsc->dbwait);
  141. s_init_wait(1);
  142. writel(0x00009C40, &dbsc->dbcmd);
  143. readl(&dbsc->dbwait);
  144. s_init_wait(1);
  145. writel(0x00009C40, &dbsc->dbcmd);
  146. readl(&dbsc->dbwait);
  147. s_init_wait(1);
  148. writel(0x00009C40, &dbsc->dbcmd);
  149. readl(&dbsc->dbwait);
  150. s_init_wait(1);
  151. writel(0x11000044, &dbsc->dbcmd);
  152. readl(&dbsc->dbwait);
  153. s_init_wait(1);
  154. writel(0x2A000000, &dbsc->dbcmd);
  155. readl(&dbsc->dbwait);
  156. s_init_wait(1);
  157. writel(0x2B000000, &dbsc->dbcmd);
  158. readl(&dbsc->dbwait);
  159. writel(0x29000004, &dbsc->dbcmd);
  160. readl(&dbsc->dbwait);
  161. writel(0x28001520, &dbsc->dbcmd);
  162. readl(&dbsc->dbwait);
  163. s_init_wait(1);
  164. writel(0x03000200, &dbsc->dbcmd);
  165. readl(&dbsc->dbwait);
  166. s_init_wait(1);
  167. writel(0x000001FF, &dbsc->dbrfcnf0);
  168. writel(0x00010C30, &dbsc->dbrfcnf1);
  169. writel(0x00000000, &dbsc->dbrfcnf2);
  170. writel(0x00000001, &dbsc->dbrfen);
  171. writel(0x00000001, &dbsc->dbacen);
  172. /* BSC */
  173. writel(0x00410400, &bsc->cs0bcr);
  174. writel(0x00410400, &bsc->cs2bcr);
  175. writel(0x00410400, &bsc->cs5bbcr);
  176. writel(0x02CB0400, &bsc->cs6abcr);
  177. writel(0x00000440, &bsc->cs0wcr);
  178. writel(0x00000440, &bsc->cs2wcr);
  179. writel(0x00000240, &bsc->cs5bwcr);
  180. writel(0x00000240, &bsc->cs6awcr);
  181. writel(0x00000005, &bsc->rbwtcnt);
  182. writel(0x00000002, &bsc->cs0wcr2);
  183. writel(0x00000002, &bsc->cs2wcr2);
  184. writel(0x00000002, &bsc->cs4wcr2);
  185. }
  186. #define GPIO_ICCR (0xE60581A0)
  187. #define ICCR_15BIT (1 << 15) /* any time 1 */
  188. #define IIC0_CONTA (1 << 7)
  189. #define IIC0_CONTB (1 << 6)
  190. #define IIC1_CONTA (1 << 5)
  191. #define IIC1_CONTB (1 << 4)
  192. #define IIC0_PS33E (1 << 1)
  193. #define IIC1_PS33E (1 << 0)
  194. #define GPIO_ICCR_DATA \
  195. (ICCR_15BIT | \
  196. IIC0_CONTA | IIC0_CONTB | IIC1_CONTA | \
  197. IIC1_CONTB | IIC0_PS33E | IIC1_PS33E)
  198. #define MSTPCR1 0xE6150134
  199. #define TMU0_MSTP125 (1 << 25)
  200. #define I2C0_MSTP116 (1 << 16)
  201. #define MSTPCR3 0xE615013C
  202. #define I2C1_MSTP323 (1 << 23)
  203. #define GETHER_MSTP309 (1 << 9)
  204. #define GPIO_SCIFA1_TXD (0xE60520C4)
  205. #define GPIO_SCIFA1_RXD (0xE60520C3)
  206. int board_early_init_f(void)
  207. {
  208. /* TMU */
  209. clrbits_le32(MSTPCR1, TMU0_MSTP125);
  210. /* GETHER */
  211. clrbits_le32(MSTPCR3, GETHER_MSTP309);
  212. /* I2C 0/1 */
  213. clrbits_le32(MSTPCR1, I2C0_MSTP116);
  214. clrbits_le32(MSTPCR3, I2C1_MSTP323);
  215. /* SCIFA1 */
  216. writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */
  217. writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */
  218. /* IICCR */
  219. writew(GPIO_ICCR_DATA, GPIO_ICCR);
  220. return 0;
  221. }
  222. DECLARE_GLOBAL_DATA_PTR;
  223. int board_init(void)
  224. {
  225. /* board id for linux */
  226. gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO800EVA;
  227. /* adress of boot parameters */
  228. gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
  229. /* Init PFC controller */
  230. r8a7740_pinmux_init();
  231. /* GETHER Enable */
  232. gpio_request(GPIO_FN_ET_CRS, NULL);
  233. gpio_request(GPIO_FN_ET_MDC, NULL);
  234. gpio_request(GPIO_FN_ET_MDIO, NULL);
  235. gpio_request(GPIO_FN_ET_TX_ER, NULL);
  236. gpio_request(GPIO_FN_ET_RX_ER, NULL);
  237. gpio_request(GPIO_FN_ET_ERXD0, NULL);
  238. gpio_request(GPIO_FN_ET_ERXD1, NULL);
  239. gpio_request(GPIO_FN_ET_ERXD2, NULL);
  240. gpio_request(GPIO_FN_ET_ERXD3, NULL);
  241. gpio_request(GPIO_FN_ET_TX_CLK, NULL);
  242. gpio_request(GPIO_FN_ET_TX_EN, NULL);
  243. gpio_request(GPIO_FN_ET_ETXD0, NULL);
  244. gpio_request(GPIO_FN_ET_ETXD1, NULL);
  245. gpio_request(GPIO_FN_ET_ETXD2, NULL);
  246. gpio_request(GPIO_FN_ET_ETXD3, NULL);
  247. gpio_request(GPIO_FN_ET_PHY_INT, NULL);
  248. gpio_request(GPIO_FN_ET_COL, NULL);
  249. gpio_request(GPIO_FN_ET_RX_DV, NULL);
  250. gpio_request(GPIO_FN_ET_RX_CLK, NULL);
  251. gpio_request(GPIO_PORT18, NULL); /* PHY_RST */
  252. gpio_direction_output(GPIO_PORT18, 1);
  253. return 0;
  254. }
  255. int dram_init(void)
  256. {
  257. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  258. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  259. return 0;
  260. }
  261. int board_late_init(void)
  262. {
  263. return 0;
  264. }
  265. void reset_cpu(ulong addr)
  266. {
  267. }