mcf5373l.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2003
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <serial.h>
  10. #include <watchdog.h>
  11. #include <command.h>
  12. #include <asm/m5329.h>
  13. #include <asm/immap_5329.h>
  14. #include <asm/io.h>
  15. #include <linux/delay.h>
  16. /* needed for astro bus: */
  17. #include <asm/uart.h>
  18. #include "astro.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. extern void uart_port_conf(void);
  21. int checkboard(void)
  22. {
  23. puts("Board: ");
  24. puts("ASTRO MCF5373L (Urmel) Board\n");
  25. return 0;
  26. }
  27. int dram_init(void)
  28. {
  29. #if !defined(CONFIG_MONITOR_IS_IN_RAM)
  30. sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
  31. /*
  32. * GPIO configuration for bus should be set correctly from reset,
  33. * so we do not care! First, set up address space: at this point,
  34. * we should be running from internal SRAM;
  35. * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
  36. * and do not care where it is
  37. */
  38. __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
  39. &sdp->cs0);
  40. __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
  41. &sdp->cs1);
  42. /*
  43. * I am not sure from the data sheet, but it seems burst length
  44. * has to be 8 for the 16 bit data bus we use;
  45. * so these values are for BL = 8
  46. */
  47. __raw_writel(0x33211530, &sdp->cfg1);
  48. __raw_writel(0x56570000, &sdp->cfg2);
  49. /* send PrechargeALL, REF and IREF remain cleared! */
  50. __raw_writel(0xE1462C02, &sdp->ctrl);
  51. udelay(1);
  52. /* refresh SDRAM twice */
  53. __raw_writel(0xE1462C04, &sdp->ctrl);
  54. udelay(1);
  55. __raw_writel(0xE1462C04, &sdp->ctrl);
  56. /* init MR */
  57. __raw_writel(0x008D0000, &sdp->mode);
  58. /* initialize EMR */
  59. __raw_writel(0x80010000, &sdp->mode);
  60. /* wait until DLL is locked */
  61. udelay(1);
  62. /*
  63. * enable automatic refresh, lock mode register,
  64. * clear iref and ipall
  65. */
  66. __raw_writel(0x71462C00, &sdp->ctrl);
  67. /* Dummy write to start SDRAM */
  68. writel(0, CONFIG_SYS_SDRAM_BASE);
  69. #endif
  70. /*
  71. * for get_ram_size() to work, both CS areas have to be
  72. * configured, i.e. CS1 has to be explicitely disabled, else
  73. * probing for memory will cause the SDRAM bus to hang!
  74. * (Do not rely on the SDCS register(s) being set to 0x00000000
  75. * during reset as stated in the data sheet.)
  76. */
  77. gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
  78. 0x80000000 - CONFIG_SYS_SDRAM_BASE);
  79. return 0;
  80. }
  81. #define UART_BASE MMAP_UART0
  82. int rs_serial_init(int port, int baud)
  83. {
  84. uart_t *uart;
  85. u32 counter;
  86. switch (port) {
  87. case 0:
  88. uart = (uart_t *)(MMAP_UART0);
  89. break;
  90. case 1:
  91. uart = (uart_t *)(MMAP_UART1);
  92. break;
  93. case 2:
  94. uart = (uart_t *)(MMAP_UART2);
  95. break;
  96. default:
  97. uart = (uart_t *)(MMAP_UART0);
  98. }
  99. uart_port_conf();
  100. /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
  101. writeb(UART_UCR_RESET_RX, &uart->ucr);
  102. writeb(UART_UCR_RESET_TX, &uart->ucr);
  103. writeb(UART_UCR_RESET_ERROR, &uart->ucr);
  104. writeb(UART_UCR_RESET_MR, &uart->ucr);
  105. __asm__ ("nop");
  106. writeb(0, &uart->uimr);
  107. /* write to CSR: RX/TX baud rate from timers */
  108. writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
  109. writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
  110. writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
  111. /* Setting up BaudRate */
  112. counter = (u32) (gd->bus_clk / (baud));
  113. counter >>= 5;
  114. /* write to CTUR: divide counter upper byte */
  115. writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1);
  116. /* write to CTLR: divide counter lower byte */
  117. writeb((u8) (counter & 0x00ff), &uart->ubg2);
  118. writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
  119. return 0;
  120. }
  121. void astro_put_char(char ch)
  122. {
  123. uart_t *uart;
  124. unsigned long timer;
  125. uart = (uart_t *)(MMAP_UART0);
  126. /*
  127. * Wait for last character to go. Timeout of 6ms should
  128. * be enough for our lowest baud rate of 2400.
  129. */
  130. timer = get_timer(0);
  131. while (get_timer(timer) < 6) {
  132. if (readb(&uart->usr) & UART_USR_TXRDY)
  133. break;
  134. }
  135. writeb(ch, &uart->utb);
  136. return;
  137. }
  138. int astro_is_char(void)
  139. {
  140. uart_t *uart;
  141. uart = (uart_t *)(MMAP_UART0);
  142. return readb(&uart->usr) & UART_USR_RXRDY;
  143. }
  144. int astro_get_char(void)
  145. {
  146. uart_t *uart;
  147. uart = (uart_t *)(MMAP_UART0);
  148. while (!(readb(&uart->usr) & UART_USR_RXRDY)) ;
  149. return readb(&uart->urb);
  150. }
  151. int misc_init_r(void)
  152. {
  153. int retval = 0;
  154. puts("Configure Xilinx FPGA...");
  155. retval = astro5373l_xilinx_load();
  156. if (!retval) {
  157. puts("failed!\n");
  158. return retval;
  159. }
  160. puts("done\n");
  161. puts("Configure Altera FPGA...");
  162. retval = astro5373l_altera_load();
  163. if (!retval) {
  164. puts("failed!\n");
  165. return retval;
  166. }
  167. puts("done\n");
  168. return retval;
  169. }