fpga.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2006
  4. * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH,
  5. * w.wegner@astro-kom.de
  6. *
  7. * based on the files by
  8. * Heiko Schocher, DENX Software Engineering, hs@denx.de
  9. * and
  10. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  11. * Keith Outwater, keith_outwater@mvis.com.
  12. */
  13. /* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */
  14. #include <common.h>
  15. #include <console.h>
  16. #include <watchdog.h>
  17. #include <altera.h>
  18. #include <ACEX1K.h>
  19. #include <spartan3.h>
  20. #include <command.h>
  21. #include <asm/immap_5329.h>
  22. #include <asm/io.h>
  23. #include "fpga.h"
  24. int altera_pre_fn(int cookie)
  25. {
  26. gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
  27. unsigned char tmp_char;
  28. unsigned short tmp_short;
  29. /* first, set the required pins to GPIO function */
  30. /* PAR_T0IN -> GPIO */
  31. tmp_char = readb(&gpiop->par_timer);
  32. tmp_char &= 0xfc;
  33. writeb(tmp_char, &gpiop->par_timer);
  34. /* all QSPI pins -> GPIO */
  35. writew(0x0000, &gpiop->par_qspi);
  36. /* U0RTS, U0CTS -> GPIO */
  37. tmp_short = __raw_readw(&gpiop->par_uart);
  38. tmp_short &= 0xfff3;
  39. __raw_writew(tmp_short, &gpiop->par_uart);
  40. /* all PWM pins -> GPIO */
  41. writeb(0x00, &gpiop->par_pwm);
  42. /* next, set data direction registers */
  43. writeb(0x01, &gpiop->pddr_timer);
  44. writeb(0x25, &gpiop->pddr_qspi);
  45. writeb(0x0c, &gpiop->pddr_uart);
  46. writeb(0x04, &gpiop->pddr_pwm);
  47. /* ensure other SPI peripherals are deselected */
  48. writeb(0x08, &gpiop->ppd_uart);
  49. writeb(0x38, &gpiop->ppd_qspi);
  50. /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
  51. writeb(0xFB, &gpiop->pclrr_uart);
  52. /* enable Altera configuration by clearing QSPI_CS2 and DT0IN */
  53. writeb(0xFE, &gpiop->pclrr_timer);
  54. writeb(0xDF, &gpiop->pclrr_qspi);
  55. return FPGA_SUCCESS;
  56. }
  57. /* Set the state of CONFIG Pin */
  58. int altera_config_fn(int assert_config, int flush, int cookie)
  59. {
  60. gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
  61. if (assert_config)
  62. writeb(0x04, &gpiop->ppd_uart);
  63. else
  64. writeb(0xFB, &gpiop->pclrr_uart);
  65. return FPGA_SUCCESS;
  66. }
  67. /* Returns the state of STATUS Pin */
  68. int altera_status_fn(int cookie)
  69. {
  70. gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
  71. if (readb(&gpiop->ppd_pwm) & 0x08)
  72. return FPGA_FAIL;
  73. return FPGA_SUCCESS;
  74. }
  75. /* Returns the state of CONF_DONE Pin */
  76. int altera_done_fn(int cookie)
  77. {
  78. gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
  79. if (readb(&gpiop->ppd_pwm) & 0x20)
  80. return FPGA_FAIL;
  81. return FPGA_SUCCESS;
  82. }
  83. /*
  84. * writes the complete buffer to the FPGA
  85. * writing the complete buffer in one function is much faster,
  86. * then calling it for every bit
  87. */
  88. int altera_write_fn(const void *buf, size_t len, int flush, int cookie)
  89. {
  90. size_t bytecount = 0;
  91. gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
  92. unsigned char *data = (unsigned char *)buf;
  93. unsigned char val = 0;
  94. int i;
  95. int len_40 = len / 40;
  96. while (bytecount < len) {
  97. val = data[bytecount++];
  98. i = 8;
  99. do {
  100. writeb(0xFB, &gpiop->pclrr_qspi);
  101. if (val & 0x01)
  102. writeb(0x01, &gpiop->ppd_qspi);
  103. else
  104. writeb(0xFE, &gpiop->pclrr_qspi);
  105. writeb(0x04, &gpiop->ppd_qspi);
  106. val >>= 1;
  107. i--;
  108. } while (i > 0);
  109. if (bytecount % len_40 == 0) {
  110. #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
  111. WATCHDOG_RESET();
  112. #endif
  113. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  114. putc('.'); /* let them know we are alive */
  115. #endif
  116. #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
  117. if (ctrlc())
  118. return FPGA_FAIL;
  119. #endif
  120. }
  121. }
  122. return FPGA_SUCCESS;
  123. }
  124. /* called, when programming is aborted */
  125. int altera_abort_fn(int cookie)
  126. {
  127. gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
  128. writeb(0x20, &gpiop->ppd_qspi);
  129. writeb(0x08, &gpiop->ppd_uart);
  130. return FPGA_SUCCESS;
  131. }
  132. /* called, when programming was succesful */
  133. int altera_post_fn(int cookie)
  134. {
  135. return altera_abort_fn(cookie);
  136. }
  137. /*
  138. * Note that these are pointers to code that is in Flash. They will be
  139. * relocated at runtime.
  140. * FIXME: relocation not yet working for coldfire, see below!
  141. */
  142. Altera_CYC2_Passive_Serial_fns altera_fns = {
  143. altera_pre_fn,
  144. altera_config_fn,
  145. altera_status_fn,
  146. altera_done_fn,
  147. altera_write_fn,
  148. altera_abort_fn,
  149. altera_post_fn
  150. };
  151. Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = {
  152. {Altera_CYC2,
  153. passive_serial,
  154. 85903,
  155. (void *)&altera_fns,
  156. NULL,
  157. 0}
  158. };
  159. /* Initialize the fpga. Return 1 on success, 0 on failure. */
  160. int astro5373l_altera_load(void)
  161. {
  162. int i;
  163. for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
  164. /*
  165. * I did not yet manage to get relocation work properly,
  166. * so set stuff here instead of static initialisation:
  167. */
  168. altera_fns.pre = altera_pre_fn;
  169. altera_fns.config = altera_config_fn;
  170. altera_fns.status = altera_status_fn;
  171. altera_fns.done = altera_done_fn;
  172. altera_fns.write = altera_write_fn;
  173. altera_fns.abort = altera_abort_fn;
  174. altera_fns.post = altera_post_fn;
  175. altera_fpga[i].iface_fns = (void *)&altera_fns;
  176. fpga_add(fpga_altera, &altera_fpga[i]);
  177. }
  178. return 1;
  179. }
  180. /* Set the FPGA's PROG_B line to the specified level */
  181. int xilinx_pgm_config_fn(int assert, int flush, int cookie)
  182. {
  183. gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
  184. if (assert)
  185. writeb(0xFB, &gpiop->pclrr_uart);
  186. else
  187. writeb(0x04, &gpiop->ppd_uart);
  188. return assert;
  189. }
  190. /*
  191. * Test the state of the active-low FPGA INIT line. Return 1 on INIT
  192. * asserted (low).
  193. */
  194. int xilinx_init_config_fn(int cookie)
  195. {
  196. gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
  197. return (readb(&gpiop->ppd_pwm) & 0x08) == 0;
  198. }
  199. /* Test the state of the active-high FPGA DONE pin */
  200. int xilinx_done_config_fn(int cookie)
  201. {
  202. gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
  203. return (readb(&gpiop->ppd_pwm) & 0x20) >> 5;
  204. }
  205. /* Abort an FPGA operation */
  206. int xilinx_abort_config_fn(int cookie)
  207. {
  208. gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
  209. /* ensure all SPI peripherals and FPGAs are deselected */
  210. writeb(0x08, &gpiop->ppd_uart);
  211. writeb(0x01, &gpiop->ppd_timer);
  212. writeb(0x38, &gpiop->ppd_qspi);
  213. return FPGA_FAIL;
  214. }
  215. /*
  216. * FPGA pre-configuration function. Just make sure that
  217. * FPGA reset is asserted to keep the FPGA from starting up after
  218. * configuration.
  219. */
  220. int xilinx_pre_config_fn(int cookie)
  221. {
  222. gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
  223. unsigned char tmp_char;
  224. unsigned short tmp_short;
  225. /* first, set the required pins to GPIO function */
  226. /* PAR_T0IN -> GPIO */
  227. tmp_char = readb(&gpiop->par_timer);
  228. tmp_char &= 0xfc;
  229. writeb(tmp_char, &gpiop->par_timer);
  230. /* all QSPI pins -> GPIO */
  231. writew(0x0000, &gpiop->par_qspi);
  232. /* U0RTS, U0CTS -> GPIO */
  233. tmp_short = __raw_readw(&gpiop->par_uart);
  234. tmp_short &= 0xfff3;
  235. __raw_writew(tmp_short, &gpiop->par_uart);
  236. /* all PWM pins -> GPIO */
  237. writeb(0x00, &gpiop->par_pwm);
  238. /* next, set data direction registers */
  239. writeb(0x01, &gpiop->pddr_timer);
  240. writeb(0x25, &gpiop->pddr_qspi);
  241. writeb(0x0c, &gpiop->pddr_uart);
  242. writeb(0x04, &gpiop->pddr_pwm);
  243. /* ensure other SPI peripherals are deselected */
  244. writeb(0x08, &gpiop->ppd_uart);
  245. writeb(0x38, &gpiop->ppd_qspi);
  246. writeb(0x01, &gpiop->ppd_timer);
  247. /* CONFIG = 0, STATUS = 0 -> FPGA in reset state */
  248. writeb(0xFB, &gpiop->pclrr_uart);
  249. /* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */
  250. writeb(0xF7, &gpiop->pclrr_uart);
  251. writeb(0xDF, &gpiop->pclrr_qspi);
  252. return 0;
  253. }
  254. /*
  255. * FPGA post configuration function. Should perform a test if FPGA is running.
  256. */
  257. int xilinx_post_config_fn(int cookie)
  258. {
  259. int rc = 0;
  260. /*
  261. * no test yet
  262. */
  263. return rc;
  264. }
  265. int xilinx_clk_config_fn(int assert_clk, int flush, int cookie)
  266. {
  267. gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
  268. if (assert_clk)
  269. writeb(0x04, &gpiop->ppd_qspi);
  270. else
  271. writeb(0xFB, &gpiop->pclrr_qspi);
  272. return assert_clk;
  273. }
  274. int xilinx_wr_config_fn(int assert_write, int flush, int cookie)
  275. {
  276. gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
  277. if (assert_write)
  278. writeb(0x01, &gpiop->ppd_qspi);
  279. else
  280. writeb(0xFE, &gpiop->pclrr_qspi);
  281. return assert_write;
  282. }
  283. int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
  284. {
  285. size_t bytecount = 0;
  286. gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
  287. unsigned char *data = (unsigned char *)buf;
  288. unsigned char val = 0;
  289. int i;
  290. int len_40 = len / 40;
  291. for (bytecount = 0; bytecount < len; bytecount++) {
  292. val = *(data++);
  293. for (i = 8; i > 0; i--) {
  294. writeb(0xFB, &gpiop->pclrr_qspi);
  295. if (val & 0x80)
  296. writeb(0x01, &gpiop->ppd_qspi);
  297. else
  298. writeb(0xFE, &gpiop->pclrr_qspi);
  299. writeb(0x04, &gpiop->ppd_qspi);
  300. val <<= 1;
  301. }
  302. if (bytecount % len_40 == 0) {
  303. #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
  304. WATCHDOG_RESET();
  305. #endif
  306. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  307. putc('.'); /* let them know we are alive */
  308. #endif
  309. #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
  310. if (ctrlc())
  311. return FPGA_FAIL;
  312. #endif
  313. }
  314. }
  315. return FPGA_SUCCESS;
  316. }
  317. /*
  318. * Note that these are pointers to code that is in Flash. They will be
  319. * relocated at runtime.
  320. * FIXME: relocation not yet working for coldfire, see below!
  321. */
  322. xilinx_spartan3_slave_serial_fns xilinx_fns = {
  323. xilinx_pre_config_fn,
  324. xilinx_pgm_config_fn,
  325. xilinx_clk_config_fn,
  326. xilinx_init_config_fn,
  327. xilinx_done_config_fn,
  328. xilinx_wr_config_fn,
  329. 0,
  330. xilinx_fastwr_config_fn
  331. };
  332. xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
  333. {xilinx_spartan3,
  334. slave_serial,
  335. XILINX_XC3S4000_SIZE,
  336. (void *)&xilinx_fns,
  337. 0,
  338. &spartan3_op}
  339. };
  340. /* Initialize the fpga. Return 1 on success, 0 on failure. */
  341. int astro5373l_xilinx_load(void)
  342. {
  343. int i;
  344. fpga_init();
  345. for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
  346. /*
  347. * I did not yet manage to get relocation work properly,
  348. * so set stuff here instead of static initialisation:
  349. */
  350. xilinx_fns.pre = xilinx_pre_config_fn;
  351. xilinx_fns.pgm = xilinx_pgm_config_fn;
  352. xilinx_fns.clk = xilinx_clk_config_fn;
  353. xilinx_fns.init = xilinx_init_config_fn;
  354. xilinx_fns.done = xilinx_done_config_fn;
  355. xilinx_fns.wr = xilinx_wr_config_fn;
  356. xilinx_fns.bwr = xilinx_fastwr_config_fn;
  357. xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
  358. fpga_add(fpga_xilinx, &xilinx_fpga[i]);
  359. }
  360. return 1;
  361. }