pci.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  5. * Marius Groeger <mgroeger@sysgo.de>
  6. *
  7. * (C) Copyright 2002
  8. * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  9. *
  10. * (C) Copyright 2003
  11. * Texas Instruments, <www.ti.com>
  12. * Kshitij Gupta <Kshitij@ti.com>
  13. *
  14. * (C) Copyright 2004
  15. * ARM Ltd.
  16. * Philippe Robin, <philippe.robin@arm.com>
  17. *
  18. * (C) Copyright 2011
  19. * Linaro
  20. * Linus Walleij <linus.walleij@linaro.org>
  21. */
  22. #include <common.h>
  23. #include <init.h>
  24. #include <log.h>
  25. #include <pci.h>
  26. #include <asm/io.h>
  27. #include <linux/bug.h>
  28. #include <linux/delay.h>
  29. #include "integrator-sc.h"
  30. #include "pci_v3.h"
  31. #define INTEGRATOR_BOOT_ROM_BASE 0x20000000
  32. #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
  33. /*
  34. * These are in the physical addresses on the CPU side, i.e.
  35. * where we read and write stuff - you don't want to try to
  36. * move these around
  37. */
  38. #define PHYS_PCI_MEM_BASE 0x40000000
  39. #define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */
  40. #define PHYS_PCI_CONFIG_BASE 0x61000000
  41. #define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */
  42. #define SZ_256M 0x10000000
  43. /*
  44. * These are in the PCI BUS address space
  45. * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor
  46. * we follow the example of the kernel, because that is the address
  47. * range that devices actually use - what would they be doing at
  48. * 0x40000000?
  49. */
  50. #define PCI_BUS_NONMEM_START 0x00000000
  51. #define PCI_BUS_NONMEM_SIZE SZ_256M
  52. #define PCI_BUS_PREMEM_START (PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE)
  53. #define PCI_BUS_PREMEM_SIZE SZ_256M
  54. #if PCI_BUS_NONMEM_START & 0x000fffff
  55. #error PCI_BUS_NONMEM_START must be megabyte aligned
  56. #endif
  57. #if PCI_BUS_PREMEM_START & 0x000fffff
  58. #error PCI_BUS_PREMEM_START must be megabyte aligned
  59. #endif
  60. /*
  61. * Initialize PCI Devices, report devices found.
  62. */
  63. #ifndef CONFIG_PCI_PNP
  64. #define PCI_ENET0_IOADDR 0x60000000 /* First card in PCI I/O space */
  65. #define PCI_ENET0_MEMADDR 0x40000000 /* First card in PCI memory space */
  66. static struct pci_config_table pci_integrator_config_table[] = {
  67. { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
  68. pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
  69. PCI_ENET0_MEMADDR,
  70. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
  71. { }
  72. };
  73. #endif /* CONFIG_PCI_PNP */
  74. /* V3 access routines */
  75. #define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
  76. #define v3_readb(o) (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o)))
  77. #define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
  78. #define v3_readw(o) (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o)))
  79. #define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
  80. #define v3_readl(o) (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o)))
  81. static unsigned long v3_open_config_window(pci_dev_t bdf, int offset)
  82. {
  83. unsigned int address, mapaddress;
  84. unsigned int busnr = PCI_BUS(bdf);
  85. unsigned int devfn = PCI_FUNC(bdf);
  86. /*
  87. * Trap out illegal values
  88. */
  89. if (offset > 255)
  90. BUG();
  91. if (busnr > 255)
  92. BUG();
  93. if (devfn > 255)
  94. BUG();
  95. if (busnr == 0) {
  96. /*
  97. * Linux calls the thing U-Boot calls "DEV" "SLOT"
  98. * instead, but it's the same 5 bits
  99. */
  100. int slot = PCI_DEV(bdf);
  101. /*
  102. * local bus segment so need a type 0 config cycle
  103. *
  104. * build the PCI configuration "address" with one-hot in
  105. * A31-A11
  106. *
  107. * mapaddress:
  108. * 3:1 = config cycle (101)
  109. * 0 = PCI A1 & A0 are 0 (0)
  110. */
  111. address = PCI_FUNC(bdf) << 8;
  112. mapaddress = V3_LB_MAP_TYPE_CONFIG;
  113. if (slot > 12)
  114. /*
  115. * high order bits are handled by the MAP register
  116. */
  117. mapaddress |= 1 << (slot - 5);
  118. else
  119. /*
  120. * low order bits handled directly in the address
  121. */
  122. address |= 1 << (slot + 11);
  123. } else {
  124. /*
  125. * not the local bus segment so need a type 1 config cycle
  126. *
  127. * address:
  128. * 23:16 = bus number
  129. * 15:11 = slot number (7:3 of devfn)
  130. * 10:8 = func number (2:0 of devfn)
  131. *
  132. * mapaddress:
  133. * 3:1 = config cycle (101)
  134. * 0 = PCI A1 & A0 from host bus (1)
  135. */
  136. mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
  137. address = (busnr << 16) | (devfn << 8);
  138. }
  139. /*
  140. * Set up base0 to see all 512Mbytes of memory space (not
  141. * prefetchable), this frees up base1 for re-use by
  142. * configuration memory
  143. */
  144. v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
  145. V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
  146. /*
  147. * Set up base1/map1 to point into configuration space.
  148. */
  149. v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
  150. V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
  151. v3_writew(V3_LB_MAP1, mapaddress);
  152. return PHYS_PCI_CONFIG_BASE + address + offset;
  153. }
  154. static void v3_close_config_window(void)
  155. {
  156. /*
  157. * Reassign base1 for use by prefetchable PCI memory
  158. */
  159. v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
  160. V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
  161. V3_LB_BASE_ENABLE);
  162. v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
  163. V3_LB_MAP_TYPE_MEM_MULTIPLE);
  164. /*
  165. * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
  166. */
  167. v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
  168. V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
  169. }
  170. static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf,
  171. int offset, unsigned char *val)
  172. {
  173. unsigned long addr;
  174. addr = v3_open_config_window(bdf, offset);
  175. *val = __raw_readb(addr);
  176. v3_close_config_window();
  177. return 0;
  178. }
  179. static int pci_integrator_read__word(struct pci_controller *hose,
  180. pci_dev_t bdf, int offset,
  181. unsigned short *val)
  182. {
  183. unsigned long addr;
  184. addr = v3_open_config_window(bdf, offset);
  185. *val = __raw_readw(addr);
  186. v3_close_config_window();
  187. return 0;
  188. }
  189. static int pci_integrator_read_dword(struct pci_controller *hose,
  190. pci_dev_t bdf, int offset,
  191. unsigned int *val)
  192. {
  193. unsigned long addr;
  194. addr = v3_open_config_window(bdf, offset);
  195. *val = __raw_readl(addr);
  196. v3_close_config_window();
  197. return 0;
  198. }
  199. static int pci_integrator_write_byte(struct pci_controller *hose,
  200. pci_dev_t bdf, int offset,
  201. unsigned char val)
  202. {
  203. unsigned long addr;
  204. addr = v3_open_config_window(bdf, offset);
  205. __raw_writeb((u8)val, addr);
  206. __raw_readb(addr);
  207. v3_close_config_window();
  208. return 0;
  209. }
  210. static int pci_integrator_write_word(struct pci_controller *hose,
  211. pci_dev_t bdf, int offset,
  212. unsigned short val)
  213. {
  214. unsigned long addr;
  215. addr = v3_open_config_window(bdf, offset);
  216. __raw_writew((u8)val, addr);
  217. __raw_readw(addr);
  218. v3_close_config_window();
  219. return 0;
  220. }
  221. static int pci_integrator_write_dword(struct pci_controller *hose,
  222. pci_dev_t bdf, int offset,
  223. unsigned int val)
  224. {
  225. unsigned long addr;
  226. addr = v3_open_config_window(bdf, offset);
  227. __raw_writel((u8)val, addr);
  228. __raw_readl(addr);
  229. v3_close_config_window();
  230. return 0;
  231. }
  232. struct pci_controller integrator_hose = {
  233. #ifndef CONFIG_PCI_PNP
  234. config_table: pci_integrator_config_table,
  235. #endif
  236. };
  237. void pci_init_board(void)
  238. {
  239. struct pci_controller *hose = &integrator_hose;
  240. u16 val;
  241. /* setting this register will take the V3 out of reset */
  242. __raw_writel(SC_PCI_PCIEN, SC_PCI);
  243. /* Wait for 230 ms (from spec) before accessing any V3 registers */
  244. mdelay(230);
  245. /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */
  246. v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16));
  247. /* Wait for the mailbox to settle */
  248. do {
  249. v3_writeb(V3_MAIL_DATA, 0xAA);
  250. v3_writeb(V3_MAIL_DATA + 4, 0x55);
  251. } while (v3_readb(V3_MAIL_DATA) != 0xAA ||
  252. v3_readb(V3_MAIL_DATA + 4) != 0x55);
  253. /* Make sure that V3 register access is not locked, if it is, unlock it */
  254. if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
  255. v3_writew(V3_SYSTEM, 0xA05F);
  256. /*
  257. * Ensure that the slave accesses from PCI are disabled while we
  258. * setup memory windows
  259. */
  260. val = v3_readw(V3_PCI_CMD);
  261. val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
  262. v3_writew(V3_PCI_CMD, val);
  263. /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
  264. val = v3_readw(V3_SYSTEM);
  265. val &= ~V3_SYSTEM_M_RST_OUT;
  266. v3_writew(V3_SYSTEM, val);
  267. /* Make all accesses from PCI space retry until we're ready for them */
  268. val = v3_readw(V3_PCI_CFG);
  269. val |= V3_PCI_CFG_M_RETRY_EN;
  270. v3_writew(V3_PCI_CFG, val);
  271. /*
  272. * Set up any V3 PCI Configuration Registers that we absolutely have to.
  273. * LB_CFG controls Local Bus protocol.
  274. * Enable LocalBus byte strobes for READ accesses too.
  275. * set bit 7 BE_IMODE and bit 6 BE_OMODE
  276. */
  277. val = v3_readw(V3_LB_CFG);
  278. val |= 0x0C0;
  279. v3_writew(V3_LB_CFG, val);
  280. /* PCI_CMD controls overall PCI operation. Enable PCI bus master. */
  281. val = v3_readw(V3_PCI_CMD);
  282. val |= V3_COMMAND_M_MASTER_EN;
  283. v3_writew(V3_PCI_CMD, val);
  284. /*
  285. * PCI_MAP0 controls where the PCI to CPU memory window is on
  286. * Local Bus
  287. */
  288. v3_writel(V3_PCI_MAP0,
  289. (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB |
  290. V3_PCI_MAP_M_REG_EN |
  291. V3_PCI_MAP_M_ENABLE));
  292. /* PCI_BASE0 is the PCI address of the start of the window */
  293. v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE);
  294. /* PCI_MAP1 is LOCAL address of the start of the window */
  295. v3_writel(V3_PCI_MAP1,
  296. (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB |
  297. V3_PCI_MAP_M_REG_EN |
  298. V3_PCI_MAP_M_ENABLE));
  299. /* PCI_BASE1 is the PCI address of the start of the window */
  300. v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE);
  301. /*
  302. * Set up memory the windows from local bus memory into PCI
  303. * configuration, I/O and Memory regions.
  304. * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this.
  305. */
  306. v3_writew(V3_LB_BASE2,
  307. v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE);
  308. v3_writew(V3_LB_MAP2, 0);
  309. /* PCI Configuration, use LB_BASE1/LB_MAP1. */
  310. /*
  311. * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1
  312. * Map first 256Mbytes as non-prefetchable via BASE0/MAP0
  313. */
  314. v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
  315. V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
  316. v3_writew(V3_LB_MAP0,
  317. v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM);
  318. /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
  319. v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
  320. V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
  321. V3_LB_BASE_ENABLE);
  322. v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
  323. V3_LB_MAP_TYPE_MEM_MULTIPLE);
  324. /* Dump PCI to local address space mappings */
  325. debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0));
  326. debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0));
  327. debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1));
  328. debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1));
  329. debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2));
  330. debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2));
  331. debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE));
  332. /*
  333. * Allow accesses to PCI Configuration space and set up A1, A0 for
  334. * type 1 config cycles
  335. */
  336. val = v3_readw(V3_PCI_CFG);
  337. val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1);
  338. val |= V3_PCI_CFG_M_AD_LOW0;
  339. v3_writew(V3_PCI_CFG, val);
  340. /* now we can allow incoming PCI MEMORY accesses */
  341. val = v3_readw(V3_PCI_CMD);
  342. val |= V3_COMMAND_M_MEM_EN;
  343. v3_writew(V3_PCI_CMD, val);
  344. /*
  345. * Set RST_OUT to take the PCI bus is out of reset, PCI devices can
  346. * now initialise.
  347. */
  348. val = v3_readw(V3_SYSTEM);
  349. val |= V3_SYSTEM_M_RST_OUT;
  350. v3_writew(V3_SYSTEM, val);
  351. /* Lock the V3 system register so that no one else can play with it */
  352. val = v3_readw(V3_SYSTEM);
  353. val |= V3_SYSTEM_M_LOCK;
  354. v3_writew(V3_SYSTEM, val);
  355. /*
  356. * Configure and register the PCI hose
  357. */
  358. hose->first_busno = 0;
  359. hose->last_busno = 0xff;
  360. /* System memory space, window 0 256 MB non-prefetchable */
  361. pci_set_region(hose->regions + 0,
  362. PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE,
  363. SZ_256M,
  364. PCI_REGION_MEM);
  365. /* System memory space, window 1 256 MB prefetchable */
  366. pci_set_region(hose->regions + 1,
  367. PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M,
  368. SZ_256M,
  369. PCI_REGION_MEM |
  370. PCI_REGION_PREFETCH);
  371. /* PCI I/O space */
  372. pci_set_region(hose->regions + 2,
  373. 0x00000000, PHYS_PCI_IO_BASE, 0x01000000,
  374. PCI_REGION_IO);
  375. /* PCI Memory - config space */
  376. pci_set_region(hose->regions + 3,
  377. 0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000,
  378. PCI_REGION_MEM);
  379. /* PCI V3 regs */
  380. pci_set_region(hose->regions + 4,
  381. 0x00000000, PHYS_PCI_V3_BASE, 0x01000000,
  382. PCI_REGION_MEM);
  383. hose->region_count = 5;
  384. pci_set_ops(hose,
  385. pci_integrator_read_byte,
  386. pci_integrator_read__word,
  387. pci_integrator_read_dword,
  388. pci_integrator_write_byte,
  389. pci_integrator_write_word,
  390. pci_integrator_write_dword);
  391. pci_register_hose(hose);
  392. pciauto_config_init(hose);
  393. pciauto_config_device(hose, 0);
  394. hose->last_busno = pci_hose_scan(hose);
  395. }