integrator-sc.h 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2011
  4. * Linaro
  5. * Linus Walleij <linus.walleij@linaro.org>
  6. * Register definitions for the System Controller (SC) and
  7. * the similar "CP Controller" found in the ARM Integrator/AP and
  8. * Integrator/CP reference designs
  9. */
  10. #ifndef __ARM_SC_H
  11. #define __ARM_SC_H
  12. #define SC_BASE 0x11000000
  13. /*
  14. * The system controller registers
  15. */
  16. #define SC_ID_OFFSET 0x00
  17. #define SC_OSC_OFFSET 0x04
  18. /* Setting this bit switches to 25 MHz mode, clear means 33 MHz */
  19. #define SC_OSC_DIVXY (1 << 8)
  20. #define SC_CTRLS_OFFSET 0x08
  21. #define SC_CTRLC_OFFSET 0x0C
  22. /* Set bits by writing CTRLS, clear bits by writing CTRLC */
  23. #define SC_CTRL_SOFTRESET (1 << 0)
  24. #define SC_CTRL_FLASHVPP (1 << 1)
  25. #define SC_CTRL_FLASHWP (1 << 2)
  26. #define SC_CTRL_UART1DTR (1 << 4)
  27. #define SC_CTRL_UART1RTS (1 << 5)
  28. #define SC_CTRL_UART0DTR (1 << 6)
  29. #define SC_CTRL_UART0RTS (1 << 7)
  30. #define SC_DEC_OFFSET 0x10
  31. #define SC_ARB_OFFSET 0x14
  32. #define SC_PCI_OFFSET 0x18
  33. #define SC_PCI_PCIEN (1 << 0)
  34. #define SC_PCI_PCIBINT_CLR (1 << 1)
  35. #define SC_LOCK_OFFSET 0x1C
  36. #define SC_LBFADDR_OFFSET 0x20
  37. #define SC_LBFCODE_OFFSET 0x24
  38. #define SC_ID (SC_BASE + SC_ID_OFFSET)
  39. #define SC_OSC (SC_BASE + SC_OSC_OFFSET)
  40. #define SC_CTRLS (SC_BASE + SC_CTRLS_OFFSET)
  41. #define SC_CTRLC (SC_BASE + SC_CTRLC_OFFSET)
  42. #define SC_DEC (SC_BASE + SC_DEC_OFFSET)
  43. #define SC_ARB (SC_BASE + SC_ARB_OFFSET)
  44. #define SC_PCI (SC_BASE + SC_PCI_OFFSET)
  45. #define SC_LOCK (SC_BASE + SC_LOCK_OFFSET)
  46. #define SC_LBFADDR (SC_BASE + SC_LBFADDR_OFFSET)
  47. #define SC_LBFCODE (SC_BASE + SC_LBFCODE_OFFSET)
  48. /*
  49. * The Integrator/CP as a smaller set of registers, at a different
  50. * offset - probably not to disturb old software.
  51. */
  52. #define CP_BASE 0xCB000000
  53. #define CP_IDFIELD_OFFSET 0x00
  54. #define CP_FLASHPROG_OFFSET 0x04
  55. #define CP_FLASHPROG_FLVPPEN (1 << 0)
  56. #define CP_FLASHPROG_FLWREN (1 << 1)
  57. #define CP_FLASHPROG_FLASHSIZE (1 << 2)
  58. #define CP_FLASHPROG_EXTRABANK (1 << 3)
  59. #define CP_INTREG_OFFSET 0x08
  60. #define CP_DECODE_OFFSET 0x0C
  61. #define CP_IDFIELD (CP_BASE + CP_ID_OFFSET)
  62. #define CP_FLASHPROG (CP_BASE + CP_FLASHPROG_OFFSET)
  63. #define CP_INTREG (CP_BASE + CP_INTREG_OFFSET)
  64. #define CP_DECODE (CP_BASE + CP_DECODE_OFFSET)
  65. #endif