arm-ebi.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2011
  4. * Linaro
  5. * Linus Walleij <linus.walleij@linaro.org>
  6. * Register definitions for the External Bus Interface (EBI)
  7. * found in the ARM Integrator AP and CP reference designs
  8. */
  9. #ifndef __ARM_EBI_H
  10. #define __ARM_EBI_H
  11. #define EBI_BASE 0x12000000
  12. #define EBI_CSR0_REG 0x00 /* CS0 = Boot ROM */
  13. #define EBI_CSR1_REG 0x04 /* CS1 = Flash */
  14. #define EBI_CSR2_REG 0x08 /* CS2 = SSRAM */
  15. #define EBI_CSR3_REG 0x0C /* CS3 = Expansion memory */
  16. /*
  17. * The four upper bits are the waitstates for each chip select
  18. * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles
  19. */
  20. #define EBI_CSR_WAIT_MASK 0xF0
  21. /* Whether memory is synchronous or asynchronous */
  22. #define EBI_CSR_SYNC_MASK 0xF7
  23. #define EBI_CSR_ASYNC 0x00
  24. #define EBI_CSR_SYNC 0x08
  25. /* Whether memory is write enabled or not */
  26. #define EBI_CSR_WREN_MASK 0xFB
  27. #define EBI_CSR_WREN_DISABLE 0x00
  28. #define EBI_CSR_WREN_ENABLE 0x04
  29. /* Memory bit width for each chip select */
  30. #define EBI_CSR_MEMSIZE_MASK 0xFC
  31. #define EBI_CSR_MEMSIZE_8BIT 0x00
  32. #define EBI_CSR_MEMSIZE_16BIT 0x01
  33. #define EBI_CSR_MEMSIZE_32BIT 0x02
  34. /*
  35. * The lock register need to be written with 0xa05f before anything in the
  36. * EBI can be changed.
  37. */
  38. #define EBI_LOCK_REG 0x20
  39. #define EBI_UNLOCK_MAGIC 0xA05F
  40. #endif