ds109.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2009-2012
  4. * Wojciech Dubowik <wojciech.dubowik@neratec.com>
  5. * Luka Perkov <luka@openwrt.org>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <miiphy.h>
  10. #include <net.h>
  11. #include <asm/setup.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/soc.h>
  14. #include <asm/arch/mpp.h>
  15. #include <linux/delay.h>
  16. #include "ds109.h"
  17. DECLARE_GLOBAL_DATA_PTR;
  18. int board_early_init_f(void)
  19. {
  20. /*
  21. * default gpio configuration
  22. * There are maximum 64 gpios controlled through 2 sets of registers
  23. * the below configuration configures mainly initial LED status
  24. */
  25. mvebu_config_gpio(DS109_OE_VAL_LOW,
  26. DS109_OE_VAL_HIGH,
  27. DS109_OE_LOW, DS109_OE_HIGH);
  28. /* Multi-Purpose Pins Functionality configuration */
  29. static const u32 kwmpp_config[] = {
  30. MPP0_SPI_SCn, /* SPI Flash */
  31. MPP1_SPI_MOSI,
  32. MPP2_SPI_SCK,
  33. MPP3_SPI_MISO,
  34. MPP4_GPIO,
  35. MPP5_GPO,
  36. MPP6_SYSRST_OUTn, /* Reset signal */
  37. MPP7_GPO,
  38. MPP8_TW_SDA, /* I2C */
  39. MPP9_TW_SCK, /* I2C */
  40. MPP10_UART0_TXD,
  41. MPP11_UART0_RXD,
  42. MPP12_GPO,
  43. MPP13_UART1_TXD,
  44. MPP14_UART1_RXD,
  45. MPP15_GPIO,
  46. MPP16_GPIO,
  47. MPP17_GPIO,
  48. MPP18_GPO,
  49. MPP19_GPO,
  50. MPP20_SATA1_ACTn,
  51. MPP21_SATA0_ACTn,
  52. MPP22_GPIO, /* HDD2 FAIL LED */
  53. MPP23_GPIO, /* HDD1 FAIL LED */
  54. MPP24_GPIO,
  55. MPP25_GPIO,
  56. MPP26_GPIO,
  57. MPP27_GPIO,
  58. MPP28_GPIO,
  59. MPP29_GPIO,
  60. MPP30_GPIO,
  61. MPP31_GPIO, /* HDD2 */
  62. MPP32_GPIO, /* FAN A */
  63. MPP33_GPIO, /* FAN B */
  64. MPP34_GPIO, /* FAN C */
  65. MPP35_GPIO, /* FAN SENSE */
  66. MPP36_GPIO,
  67. MPP37_GPIO,
  68. MPP38_GPIO,
  69. MPP39_GPIO,
  70. MPP40_GPIO,
  71. MPP41_GPIO,
  72. MPP42_GPIO,
  73. MPP43_GPIO,
  74. MPP44_GPIO,
  75. MPP45_GPIO,
  76. MPP46_GPIO,
  77. MPP47_GPIO,
  78. MPP48_GPIO,
  79. MPP49_GPIO,
  80. 0
  81. };
  82. kirkwood_mpp_conf(kwmpp_config, NULL);
  83. return 0;
  84. }
  85. int board_init(void)
  86. {
  87. /* address of boot parameters */
  88. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  89. return 0;
  90. }
  91. /* Synology reset uses UART */
  92. #include <ns16550.h>
  93. #define SOFTWARE_SHUTDOWN 0x31
  94. #define SOFTWARE_REBOOT 0x43
  95. #define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
  96. void reset_misc(void)
  97. {
  98. int b_d;
  99. printf("Synology reset...");
  100. udelay(50000);
  101. b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2,
  102. CONFIG_SYS_NS16550_CLK, 9600);
  103. NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d);
  104. NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT);
  105. }
  106. /* Support old kernels */
  107. void setup_board_tags(struct tag **in_params)
  108. {
  109. unsigned int boardId;
  110. struct tag *params;
  111. struct tag_mv_uboot *t;
  112. int i;
  113. printf("Synology board tags...");
  114. params = *in_params;
  115. t = (struct tag_mv_uboot *)&params->u;
  116. t->uboot_version = VER_NUM;
  117. boardId = SYNO_DS109_ID;
  118. t->uboot_version |= boardId;
  119. t->tclk = CONFIG_SYS_TCLK;
  120. t->sysclk = CONFIG_SYS_TCLK*2;
  121. t->isusbhost = 1;
  122. for (i = 0; i < 4; i++) {
  123. memset(t->macaddr[i], 0, sizeof(t->macaddr[i]));
  124. t->mtu[i] = 0;
  125. }
  126. params->hdr.tag = ATAG_MV_UBOOT;
  127. params->hdr.size = tag_size(tag_mv_uboot);
  128. params = tag_next(params);
  129. *in_params = params;
  130. }
  131. #ifdef CONFIG_RESET_PHY_R
  132. /* Configure and enable MV88E1116 PHY */
  133. void reset_phy(void)
  134. {
  135. u16 reg;
  136. u16 devadr;
  137. char *name = "egiga0";
  138. if (miiphy_set_current_dev(name))
  139. return;
  140. /* command to read PHY dev address */
  141. if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
  142. printf("Error: 88E1116 could not read PHY dev address\n");
  143. return;
  144. }
  145. /*
  146. * Enable RGMII delay on Tx and Rx for CPU port
  147. * Ref: sec 4.7.2 of chip datasheet
  148. */
  149. miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
  150. miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
  151. reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
  152. miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
  153. miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
  154. /* reset the phy */
  155. miiphy_reset(name, devadr);
  156. printf("88E1116 Initialized on %s\n", name);
  157. }
  158. #endif /* CONFIG_RESET_PHY_R */