openrd.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Net Insight <www.netinsight.net>
  5. * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
  6. *
  7. * Based on sheevaplug.c:
  8. * (C) Copyright 2009
  9. * Marvell Semiconductor <www.marvell.com>
  10. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  11. */
  12. #include <common.h>
  13. #include <init.h>
  14. #include <miiphy.h>
  15. #include <net.h>
  16. #include <asm/mach-types.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/soc.h>
  19. #include <asm/arch/mpp.h>
  20. #include "openrd.h"
  21. DECLARE_GLOBAL_DATA_PTR;
  22. int board_early_init_f(void)
  23. {
  24. /*
  25. * default gpio configuration
  26. * There are maximum 64 gpios controlled through 2 sets of registers
  27. * the below configuration configures mainly initial LED status
  28. */
  29. mvebu_config_gpio(OPENRD_OE_VAL_LOW,
  30. OPENRD_OE_VAL_HIGH,
  31. OPENRD_OE_LOW, OPENRD_OE_HIGH);
  32. /* Multi-Purpose Pins Functionality configuration */
  33. static const u32 kwmpp_config[] = {
  34. MPP0_NF_IO2,
  35. MPP1_NF_IO3,
  36. MPP2_NF_IO4,
  37. MPP3_NF_IO5,
  38. MPP4_NF_IO6,
  39. MPP5_NF_IO7,
  40. MPP6_SYSRST_OUTn,
  41. MPP7_GPO,
  42. MPP8_TW_SDA,
  43. MPP9_TW_SCK,
  44. MPP10_UART0_TXD,
  45. MPP11_UART0_RXD,
  46. MPP12_SD_CLK,
  47. MPP13_SD_CMD, /* Alt UART1_TXD */
  48. MPP14_SD_D0, /* Alt UART1_RXD */
  49. MPP15_SD_D1,
  50. MPP16_SD_D2,
  51. MPP17_SD_D3,
  52. MPP18_NF_IO0,
  53. MPP19_NF_IO1,
  54. MPP20_GE1_0,
  55. MPP21_GE1_1,
  56. MPP22_GE1_2,
  57. MPP23_GE1_3,
  58. MPP24_GE1_4,
  59. MPP25_GE1_5,
  60. MPP26_GE1_6,
  61. MPP27_GE1_7,
  62. MPP28_GPIO,
  63. MPP29_TSMP9,
  64. MPP30_GE1_10,
  65. MPP31_GE1_11,
  66. MPP32_GE1_12,
  67. MPP33_GE1_13,
  68. MPP34_GPIO, /* UART1 / SD sel */
  69. MPP35_TDM_CH0_TX_QL,
  70. MPP36_TDM_SPI_CS1,
  71. MPP37_TDM_CH2_TX_QL,
  72. MPP38_TDM_CH2_RX_QL,
  73. MPP39_AUDIO_I2SBCLK,
  74. MPP40_AUDIO_I2SDO,
  75. MPP41_AUDIO_I2SLRC,
  76. MPP42_AUDIO_I2SMCLK,
  77. MPP43_AUDIO_I2SDI,
  78. MPP44_AUDIO_EXTCLK,
  79. MPP45_TDM_PCLK,
  80. MPP46_TDM_FS,
  81. MPP47_TDM_DRX,
  82. MPP48_TDM_DTX,
  83. MPP49_TDM_CH0_RX_QL,
  84. 0
  85. };
  86. kirkwood_mpp_conf(kwmpp_config, NULL);
  87. return 0;
  88. }
  89. int board_init(void)
  90. {
  91. /*
  92. * arch number of board
  93. */
  94. #if defined(CONFIG_BOARD_IS_OPENRD_BASE)
  95. gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
  96. #elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
  97. gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
  98. #elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
  99. gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
  100. #endif
  101. /* adress of boot parameters */
  102. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  103. return 0;
  104. }
  105. #ifdef CONFIG_RESET_PHY_R
  106. /* Configure and enable MV88E1116/88E1121 PHY */
  107. void mv_phy_init(char *name)
  108. {
  109. u16 reg;
  110. u16 devadr;
  111. if (miiphy_set_current_dev(name))
  112. return;
  113. /* command to read PHY dev address */
  114. if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
  115. printf("Err..%s could not read PHY dev address\n", __func__);
  116. return;
  117. }
  118. /*
  119. * Enable RGMII delay on Tx and Rx for CPU port
  120. * Ref: sec 4.7.2 of chip datasheet
  121. */
  122. miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
  123. miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
  124. reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
  125. miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
  126. miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
  127. /* reset the phy */
  128. miiphy_reset(name, devadr);
  129. printf(PHY_NO" Initialized on %s\n", name);
  130. }
  131. void reset_phy(void)
  132. {
  133. mv_phy_init("egiga0");
  134. #ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
  135. /* Kirkwood ethernet driver is written with the assumption that in case
  136. * of multiple PHYs, their addresses are consecutive. But unfortunately
  137. * in case of OpenRD-Client, PHY addresses are not consecutive.*/
  138. miiphy_write("egiga1", 0xEE, 0xEE, 24);
  139. #endif
  140. #if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
  141. defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
  142. /* configure and initialize both PHY's */
  143. mv_phy_init("egiga1");
  144. #endif
  145. }
  146. #endif /* CONFIG_RESET_PHY_R */