board.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <env.h>
  8. #include <i2c.h>
  9. #include <init.h>
  10. #include <mmc.h>
  11. #include <phy.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/soc.h>
  15. #include <linux/delay.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. /* IO expander I2C device */
  18. #define I2C_IO_EXP_ADDR 0x22
  19. #define I2C_IO_CFG_REG_0 0x6
  20. #define I2C_IO_DATA_OUT_REG_0 0x2
  21. #define I2C_IO_REG_0_SATA_OFF 2
  22. #define I2C_IO_REG_0_USB_H_OFF 1
  23. /* The pin control values are the same for DB and Espressobin */
  24. #define PINCTRL_NB_REG_VALUE 0x000173fa
  25. #define PINCTRL_SB_REG_VALUE 0x00007a23
  26. /* Ethernet switch registers */
  27. /* SMI addresses for multi-chip mode */
  28. #define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p))
  29. #define MVEBU_SW_G2_SMI_ADDR (28)
  30. /* Multi-chip mode */
  31. #define MVEBU_SW_SMI_DATA_REG (1)
  32. #define MVEBU_SW_SMI_CMD_REG (0)
  33. #define SW_SMI_CMD_REG_ADDR_OFF 0
  34. #define SW_SMI_CMD_DEV_ADDR_OFF 5
  35. #define SW_SMI_CMD_SMI_OP_OFF 10
  36. #define SW_SMI_CMD_SMI_MODE_OFF 12
  37. #define SW_SMI_CMD_SMI_BUSY_OFF 15
  38. /* Single-chip mode */
  39. /* Switch Port Registers */
  40. #define MVEBU_SW_LINK_CTRL_REG (1)
  41. #define MVEBU_SW_PORT_CTRL_REG (4)
  42. #define MVEBU_SW_PORT_BASE_VLAN (6)
  43. /* Global 2 Registers */
  44. #define MVEBU_G2_SMI_PHY_CMD_REG (24)
  45. #define MVEBU_G2_SMI_PHY_DATA_REG (25)
  46. /*
  47. * Memory Controller Registers
  48. *
  49. * Assembled based on public information:
  50. * https://gitlab.nic.cz/turris/mox-boot-builder/-/blob/master/wtmi/main.c#L332-336
  51. * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-18.12/drivers/mv_ddr_mc6.h#L309-L332
  52. *
  53. * And checked against the written register values for the various topologies:
  54. * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-atf-mainline/a3700/mv_ddr_tim.h
  55. */
  56. #define A3700_CH0_MC_CTRL2_REG MVEBU_REGISTER(0x002c4)
  57. #define A3700_MC_CTRL2_SDRAM_TYPE_MASK 0xf
  58. #define A3700_MC_CTRL2_SDRAM_TYPE_OFFS 4
  59. #define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
  60. #define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
  61. int board_early_init_f(void)
  62. {
  63. return 0;
  64. }
  65. int board_init(void)
  66. {
  67. /* adress of boot parameters */
  68. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  69. return 0;
  70. }
  71. #ifdef CONFIG_BOARD_LATE_INIT
  72. int board_late_init(void)
  73. {
  74. struct mmc *mmc_dev;
  75. bool ddr4, emmc;
  76. if (env_get("fdtfile"))
  77. return 0;
  78. if (!of_machine_is_compatible("globalscale,espressobin"))
  79. return 0;
  80. /* If the memory controller has been configured for DDR4, we're running on v7 */
  81. ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS)
  82. & A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4;
  83. /* eMMC is mmc dev num 1 */
  84. mmc_dev = find_mmc_device(1);
  85. emmc = (mmc_dev && mmc_init(mmc_dev) == 0);
  86. if (ddr4 && emmc)
  87. env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb");
  88. else if (ddr4)
  89. env_set("fdtfile", "marvell/armada-3720-espressobin-v7.dtb");
  90. else if (emmc)
  91. env_set("fdtfile", "marvell/armada-3720-espressobin-emmc.dtb");
  92. else
  93. env_set("fdtfile", "marvell/armada-3720-espressobin.dtb");
  94. return 0;
  95. }
  96. #endif
  97. /* Board specific AHCI / SATA enable code */
  98. int board_ahci_enable(void)
  99. {
  100. struct udevice *dev;
  101. int ret;
  102. u8 buf[8];
  103. /* Only DB requres this configuration */
  104. if (!of_machine_is_compatible("marvell,armada-3720-db"))
  105. return 0;
  106. /* Configure IO exander PCA9555: 7bit address 0x22 */
  107. ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
  108. if (ret) {
  109. printf("Cannot find PCA9555: %d\n", ret);
  110. return 0;
  111. }
  112. ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
  113. if (ret) {
  114. printf("Failed to read IO expander value via I2C\n");
  115. return -EIO;
  116. }
  117. /*
  118. * Enable SATA power via IO expander connected via I2C by setting
  119. * the corresponding bit to output mode to enable power for SATA
  120. */
  121. buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
  122. ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
  123. if (ret) {
  124. printf("Failed to set IO expander via I2C\n");
  125. return -EIO;
  126. }
  127. return 0;
  128. }
  129. /* Board specific xHCI enable code */
  130. int board_xhci_enable(fdt_addr_t base)
  131. {
  132. struct udevice *dev;
  133. int ret;
  134. u8 buf[8];
  135. /* Only DB requres this configuration */
  136. if (!of_machine_is_compatible("marvell,armada-3720-db"))
  137. return 0;
  138. /* Configure IO exander PCA9555: 7bit address 0x22 */
  139. ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
  140. if (ret) {
  141. printf("Cannot find PCA9555: %d\n", ret);
  142. return 0;
  143. }
  144. printf("Enable USB VBUS\n");
  145. /*
  146. * Read configuration (direction) and set VBUS pin as output
  147. * (reset pin = output)
  148. */
  149. ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
  150. if (ret) {
  151. printf("Failed to read IO expander value via I2C\n");
  152. return -EIO;
  153. }
  154. buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
  155. ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
  156. if (ret) {
  157. printf("Failed to set IO expander via I2C\n");
  158. return -EIO;
  159. }
  160. /* Read VBUS output value and disable it */
  161. ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
  162. if (ret) {
  163. printf("Failed to read IO expander value via I2C\n");
  164. return -EIO;
  165. }
  166. buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
  167. ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
  168. if (ret) {
  169. printf("Failed to set IO expander via I2C\n");
  170. return -EIO;
  171. }
  172. /*
  173. * Required delay for configuration to settle - must wait for
  174. * power on port is disabled in case VBUS signal was high,
  175. * required 3 seconds delay to let VBUS signal fully settle down
  176. */
  177. mdelay(3000);
  178. /* Enable VBUS power: Set output value of VBUS pin as enabled */
  179. buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
  180. ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
  181. if (ret) {
  182. printf("Failed to set IO expander via I2C\n");
  183. return -EIO;
  184. }
  185. mdelay(500); /* required delay to let output value settle */
  186. return 0;
  187. }
  188. /* Helper function for accessing switch devices in multi-chip connection mode */
  189. static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
  190. int smi_addr, int reg, u16 value)
  191. {
  192. u16 smi_cmd = 0;
  193. if (bus->write(bus, dev_smi_addr, 0,
  194. MVEBU_SW_SMI_DATA_REG, value) != 0) {
  195. printf("Error writing to the PHY addr=%02x reg=%02x\n",
  196. smi_addr, reg);
  197. return -EFAULT;
  198. }
  199. smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
  200. (1 << SW_SMI_CMD_SMI_MODE_OFF) |
  201. (1 << SW_SMI_CMD_SMI_OP_OFF) |
  202. (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
  203. (reg << SW_SMI_CMD_REG_ADDR_OFF);
  204. if (bus->write(bus, dev_smi_addr, 0,
  205. MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
  206. printf("Error writing to the PHY addr=%02x reg=%02x\n",
  207. smi_addr, reg);
  208. return -EFAULT;
  209. }
  210. return 0;
  211. }
  212. /* Bring-up board-specific network stuff */
  213. int board_network_enable(struct mii_dev *bus)
  214. {
  215. if (!of_machine_is_compatible("globalscale,espressobin"))
  216. return 0;
  217. /*
  218. * FIXME: remove this code once Topaz driver gets available
  219. * A3720 Community Board Only
  220. * Configure Topaz switch (88E6341)
  221. * Restrict output to ports 1,2,3 only from port 0 (CPU)
  222. * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
  223. */
  224. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
  225. MVEBU_SW_PORT_BASE_VLAN, BIT(0));
  226. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
  227. MVEBU_SW_PORT_BASE_VLAN, BIT(0));
  228. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
  229. MVEBU_SW_PORT_BASE_VLAN, BIT(0));
  230. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
  231. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  232. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
  233. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  234. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
  235. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  236. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
  237. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  238. /* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
  239. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
  240. MVEBU_SW_LINK_CTRL_REG, 0xe002);
  241. /* Power up PHY 1, 2, 3 (through Global 2 registers) */
  242. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  243. MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
  244. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  245. MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
  246. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  247. MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
  248. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  249. MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);
  250. return 0;
  251. }
  252. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  253. int ft_board_setup(void *blob, struct bd_info *bd)
  254. {
  255. int ret;
  256. int spi_off;
  257. int parts_off;
  258. int part_off;
  259. /* Fill SPI MTD partitions for Linux kernel on Espressobin */
  260. if (!of_machine_is_compatible("globalscale,espressobin"))
  261. return 0;
  262. spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
  263. if (spi_off < 0)
  264. return 0;
  265. /* Do not touch partitions if they are already defined */
  266. if (fdt_subnode_offset(blob, spi_off, "partitions") >= 0)
  267. return 0;
  268. parts_off = fdt_add_subnode(blob, spi_off, "partitions");
  269. if (parts_off < 0) {
  270. printf("Can't add partitions node: %s\n", fdt_strerror(parts_off));
  271. return 0;
  272. }
  273. ret = fdt_setprop_string(blob, parts_off, "compatible", "fixed-partitions");
  274. if (ret < 0) {
  275. printf("Can't set compatible property: %s\n", fdt_strerror(ret));
  276. return 0;
  277. }
  278. ret = fdt_setprop_u32(blob, parts_off, "#address-cells", 1);
  279. if (ret < 0) {
  280. printf("Can't set #address-cells property: %s\n", fdt_strerror(ret));
  281. return 0;
  282. }
  283. ret = fdt_setprop_u32(blob, parts_off, "#size-cells", 1);
  284. if (ret < 0) {
  285. printf("Can't set #size-cells property: %s\n", fdt_strerror(ret));
  286. return 0;
  287. }
  288. /* Add u-boot-env partition */
  289. part_off = fdt_add_subnode(blob, parts_off, "partition@u-boot-env");
  290. if (part_off < 0) {
  291. printf("Can't add partition@u-boot-env node: %s\n", fdt_strerror(part_off));
  292. return 0;
  293. }
  294. ret = fdt_setprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
  295. if (ret < 0) {
  296. printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
  297. return 0;
  298. }
  299. ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_SIZE);
  300. if (ret < 0) {
  301. printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
  302. return 0;
  303. }
  304. ret = fdt_setprop_string(blob, part_off, "label", "u-boot-env");
  305. if (ret < 0) {
  306. printf("Can't set partition@u-boot-env label property: %s\n", fdt_strerror(ret));
  307. return 0;
  308. }
  309. /* Add firmware partition */
  310. part_off = fdt_add_subnode(blob, parts_off, "partition@firmware");
  311. if (part_off < 0) {
  312. printf("Can't add partition@firmware node: %s\n", fdt_strerror(part_off));
  313. return 0;
  314. }
  315. ret = fdt_setprop_u32(blob, part_off, "reg", 0);
  316. if (ret < 0) {
  317. printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
  318. return 0;
  319. }
  320. ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
  321. if (ret < 0) {
  322. printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
  323. return 0;
  324. }
  325. ret = fdt_setprop_string(blob, part_off, "label", "firmware");
  326. if (ret < 0) {
  327. printf("Can't set partition@firmware label property: %s\n", fdt_strerror(ret));
  328. return 0;
  329. }
  330. return 0;
  331. }
  332. #endif