kwbimage.cfg 4.8 KB

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  1. # SPDX-License-Identifier: GPL-2.0+
  2. #
  3. # Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
  4. #
  5. # Based on Kirkwood support:
  6. # (C) Copyright 2009
  7. # Marvell Semiconductor <www.marvell.com>
  8. # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  9. # Refer doc/README.kwbimage for more details about how-to configure
  10. # and create kirkwood boot image
  11. #
  12. # Boot Media configurations
  13. BOOT_FROM spi # Boot from SPI flash
  14. # SOC registers configuration using bootrom header extension
  15. # Maximum KWBIMAGE_MAX_CONFIG configurations allowed
  16. # Configure RGMII-0 interface pad voltage to 1.8V
  17. DATA 0xFFD100e0 0x1B1B1B9B
  18. #Dram initalization for SINGLE x16 CL=5 @ 400MHz
  19. DATA 0xFFD01400 0x43000618 # DDR Configuration register
  20. # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
  21. # bit23-14: zero
  22. # bit24: 1= enable exit self refresh mode on DDR access
  23. # bit25: 1 required
  24. # bit29-26: zero
  25. # bit31-30: 01
  26. DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
  27. # bit 4: 0=addr/cmd in smame cycle
  28. # bit 5: 0=clk is driven during self refresh, we don't care for APX
  29. # bit 6: 0=use recommended falling edge of clk for addr/cmd
  30. # bit14: 0=input buffer always powered up
  31. # bit18: 1=cpu lock transaction enabled
  32. # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
  33. # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
  34. # bit30-28: 3 required
  35. # bit31: 0=no additional STARTBURST delay
  36. DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
  37. # bit7-4: TRCD
  38. # bit11- 8: TRP
  39. # bit15-12: TWR
  40. # bit19-16: TWTR
  41. # bit20: TRAS msb
  42. # bit23-21: 0x0
  43. # bit27-24: TRRD
  44. # bit31-28: TRTP
  45. DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
  46. # bit6-0: TRFC
  47. # bit8-7: TR2R
  48. # bit10-9: TR2W
  49. # bit12-11: TW2W
  50. # bit31-13: zero required
  51. DATA 0xFFD01410 0x0000000C # DDR Address Control
  52. # bit1-0: 00, Cs0width=x8
  53. # bit3-2: 11, Cs0size=1Gb
  54. # bit5-4: 00, Cs2width=nonexistent
  55. # bit7-6: 00, Cs1size =nonexistent
  56. # bit9-8: 00, Cs2width=nonexistent
  57. # bit11-10: 00, Cs2size =nonexistent
  58. # bit13-12: 00, Cs3width=nonexistent
  59. # bit15-14: 00, Cs3size =nonexistent
  60. # bit16: 0, Cs0AddrSel
  61. # bit17: 0, Cs1AddrSel
  62. # bit18: 0, Cs2AddrSel
  63. # bit19: 0, Cs3AddrSel
  64. # bit31-20: 0 required
  65. DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
  66. # bit0: 0, OpenPage enabled
  67. # bit31-1: 0 required
  68. DATA 0xFFD01418 0x00000000 # DDR Operation
  69. # bit3-0: 0x0, DDR cmd
  70. # bit31-4: 0 required
  71. DATA 0xFFD0141C 0x00000632 # DDR Mode
  72. # bit2-0: 2, BurstLen=2 required
  73. # bit3: 0, BurstType=0 required
  74. # bit6-4: 4, CL=5
  75. # bit7: 0, TestMode=0 normal
  76. # bit8: 0, DLL reset=0 normal
  77. # bit11-9: 6, auto-precharge write recovery ????????????
  78. # bit12: 0, PD must be zero
  79. # bit31-13: 0 required
  80. DATA 0xFFD01420 0x00000004 # DDR Extended Mode
  81. # bit0: 0, DDR DLL enabled
  82. # bit1: 1, DDR drive strenght reduced
  83. # bit2: 1, DDR ODT control lsd enabled
  84. # bit5-3: 000, required
  85. # bit6: 1, DDR ODT control msb, enabled
  86. # bit9-7: 000, required
  87. # bit10: 0, differential DQS enabled
  88. # bit11: 0, required
  89. # bit12: 0, DDR output buffer enabled
  90. # bit31-13: 0 required
  91. DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
  92. # bit2-0: 111, required
  93. # bit3 : 1 , MBUS Burst Chop disabled
  94. # bit6-4: 111, required
  95. # bit7 : 1 , D2P Latency enabled
  96. # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
  97. # bit9 : 0 , no half clock cycle addition to dataout
  98. # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
  99. # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
  100. # bit15-12: 1111 required
  101. # bit31-16: 0 required
  102. DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
  103. DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
  104. DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
  105. DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
  106. # bit0: 1, Window enabled
  107. # bit1: 0, Write Protect disabled
  108. # bit3-2: 00, CS0 hit selected
  109. # bit23-4: ones, required
  110. # bit31-24: 0x07, Size (i.e. 128MB)
  111. DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
  112. DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
  113. DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
  114. DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
  115. # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
  116. # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
  117. DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
  118. # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
  119. # bit3-2: 01, ODT1 active NEVER!
  120. # bit31-4: zero, required
  121. DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
  122. # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
  123. # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
  124. # bit11-10:1, DQ_ODTSel. ODT select turned on
  125. DATA 0xFFD01480 0x00000001 # DDR Initialization Control
  126. #bit0=1, enable DDR init upon this register write
  127. # End of Header extension
  128. DATA 0x0 0x0