turris_omnia.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
  4. * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
  5. *
  6. * Derived from the code for
  7. * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <i2c.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <miiphy.h>
  15. #include <net.h>
  16. #include <netdev.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/soc.h>
  20. #include <dm/uclass.h>
  21. #include <fdt_support.h>
  22. #include <time.h>
  23. #include <linux/bitops.h>
  24. #include <u-boot/crc.h>
  25. # include <atsha204a-i2c.h>
  26. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  27. #include <../serdes/a38x/high_speed_env_spec.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
  30. #define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
  31. #define OMNIA_I2C_MCU_CHIP_LEN 1
  32. #define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
  33. #define OMNIA_I2C_EEPROM_CHIP_LEN 2
  34. #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
  35. enum mcu_commands {
  36. CMD_GET_STATUS_WORD = 0x01,
  37. CMD_GET_RESET = 0x09,
  38. CMD_WATCHDOG_STATE = 0x0b,
  39. };
  40. enum status_word_bits {
  41. CARD_DET_STSBIT = 0x0010,
  42. MSATA_IND_STSBIT = 0x0020,
  43. };
  44. #define OMNIA_ATSHA204_OTP_VERSION 0
  45. #define OMNIA_ATSHA204_OTP_SERIAL 1
  46. #define OMNIA_ATSHA204_OTP_MAC0 3
  47. #define OMNIA_ATSHA204_OTP_MAC1 4
  48. /*
  49. * Those values and defines are taken from the Marvell U-Boot version
  50. * "u-boot-2013.01-2014_T3.0"
  51. */
  52. #define OMNIA_GPP_OUT_ENA_LOW \
  53. (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
  54. BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
  55. BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
  56. #define OMNIA_GPP_OUT_ENA_MID \
  57. (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
  58. BIT(16) | BIT(17) | BIT(18)))
  59. #define OMNIA_GPP_OUT_VAL_LOW 0x0
  60. #define OMNIA_GPP_OUT_VAL_MID 0x0
  61. #define OMNIA_GPP_POL_LOW 0x0
  62. #define OMNIA_GPP_POL_MID 0x0
  63. static struct serdes_map board_serdes_map_pex[] = {
  64. {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  65. {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  66. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  67. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  68. {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  69. {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  70. };
  71. static struct serdes_map board_serdes_map_sata[] = {
  72. {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  73. {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  74. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  75. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  76. {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  77. {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  78. };
  79. static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
  80. uint offset_len)
  81. {
  82. struct udevice *bus, *dev;
  83. int ret;
  84. ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
  85. if (ret) {
  86. printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
  87. OMNIA_I2C_BUS_NAME, ret);
  88. return NULL;
  89. }
  90. ret = i2c_get_chip(bus, addr, offset_len, &dev);
  91. if (ret) {
  92. printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
  93. name, ret);
  94. return NULL;
  95. }
  96. return dev;
  97. }
  98. static int omnia_mcu_read(u8 cmd, void *buf, int len)
  99. {
  100. struct udevice *chip;
  101. chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
  102. OMNIA_I2C_MCU_CHIP_LEN);
  103. if (!chip)
  104. return -ENODEV;
  105. return dm_i2c_read(chip, cmd, buf, len);
  106. }
  107. #ifndef CONFIG_SPL_BUILD
  108. static int omnia_mcu_write(u8 cmd, const void *buf, int len)
  109. {
  110. struct udevice *chip;
  111. chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
  112. OMNIA_I2C_MCU_CHIP_LEN);
  113. if (!chip)
  114. return -ENODEV;
  115. return dm_i2c_write(chip, cmd, buf, len);
  116. }
  117. static bool disable_mcu_watchdog(void)
  118. {
  119. int ret;
  120. puts("Disabling MCU watchdog... ");
  121. ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
  122. if (ret) {
  123. printf("omnia_mcu_write failed: %i\n", ret);
  124. return false;
  125. }
  126. puts("disabled\n");
  127. return true;
  128. }
  129. #endif
  130. static bool omnia_detect_sata(void)
  131. {
  132. int ret;
  133. u16 stsword;
  134. puts("MiniPCIe/mSATA card detection... ");
  135. ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
  136. if (ret) {
  137. printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
  138. ret);
  139. return false;
  140. }
  141. if (!(stsword & CARD_DET_STSBIT)) {
  142. puts("none\n");
  143. return false;
  144. }
  145. if (stsword & MSATA_IND_STSBIT)
  146. puts("mSATA\n");
  147. else
  148. puts("MiniPCIe\n");
  149. return stsword & MSATA_IND_STSBIT ? true : false;
  150. }
  151. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  152. {
  153. if (omnia_detect_sata()) {
  154. *serdes_map_array = board_serdes_map_sata;
  155. *count = ARRAY_SIZE(board_serdes_map_sata);
  156. } else {
  157. *serdes_map_array = board_serdes_map_pex;
  158. *count = ARRAY_SIZE(board_serdes_map_pex);
  159. }
  160. return 0;
  161. }
  162. struct omnia_eeprom {
  163. u32 magic;
  164. u32 ramsize;
  165. char region[4];
  166. u32 crc;
  167. };
  168. static bool omnia_read_eeprom(struct omnia_eeprom *oep)
  169. {
  170. struct udevice *chip;
  171. u32 crc;
  172. int ret;
  173. chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
  174. OMNIA_I2C_EEPROM_CHIP_LEN);
  175. if (!chip)
  176. return false;
  177. ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
  178. if (ret) {
  179. printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
  180. return false;
  181. }
  182. if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
  183. printf("bad EEPROM magic number (%08x, should be %08x)\n",
  184. oep->magic, OMNIA_I2C_EEPROM_MAGIC);
  185. return false;
  186. }
  187. crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
  188. if (crc != oep->crc) {
  189. printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
  190. oep->crc, crc);
  191. return false;
  192. }
  193. return true;
  194. }
  195. static int omnia_get_ram_size_gb(void)
  196. {
  197. static int ram_size;
  198. struct omnia_eeprom oep;
  199. if (!ram_size) {
  200. /* Get the board config from EEPROM */
  201. if (omnia_read_eeprom(&oep)) {
  202. debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
  203. if (oep.ramsize == 0x2)
  204. ram_size = 2;
  205. else
  206. ram_size = 1;
  207. } else {
  208. /* Hardcoded fallback */
  209. puts("Memory config from EEPROM read failed!\n");
  210. puts("Falling back to default 1 GiB!\n");
  211. ram_size = 1;
  212. }
  213. }
  214. return ram_size;
  215. }
  216. /*
  217. * Define the DDR layout / topology here in the board file. This will
  218. * be used by the DDR3 init code in the SPL U-Boot version to configure
  219. * the DDR3 controller.
  220. */
  221. static struct mv_ddr_topology_map board_topology_map_1g = {
  222. DEBUG_LEVEL_ERROR,
  223. 0x1, /* active interfaces */
  224. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  225. { { { {0x1, 0, 0, 0},
  226. {0x1, 0, 0, 0},
  227. {0x1, 0, 0, 0},
  228. {0x1, 0, 0, 0},
  229. {0x1, 0, 0, 0} },
  230. SPEED_BIN_DDR_1600K, /* speed_bin */
  231. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  232. MV_DDR_DIE_CAP_4GBIT, /* mem_size */
  233. MV_DDR_FREQ_800, /* frequency */
  234. 0, 0, /* cas_wl cas_l */
  235. MV_DDR_TEMP_NORMAL, /* temperature */
  236. MV_DDR_TIM_2T} }, /* timing */
  237. BUS_MASK_32BIT, /* Busses mask */
  238. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  239. { {0} }, /* raw spd data */
  240. {0} /* timing parameters */
  241. };
  242. static struct mv_ddr_topology_map board_topology_map_2g = {
  243. DEBUG_LEVEL_ERROR,
  244. 0x1, /* active interfaces */
  245. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  246. { { { {0x1, 0, 0, 0},
  247. {0x1, 0, 0, 0},
  248. {0x1, 0, 0, 0},
  249. {0x1, 0, 0, 0},
  250. {0x1, 0, 0, 0} },
  251. SPEED_BIN_DDR_1600K, /* speed_bin */
  252. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  253. MV_DDR_DIE_CAP_8GBIT, /* mem_size */
  254. MV_DDR_FREQ_800, /* frequency */
  255. 0, 0, /* cas_wl cas_l */
  256. MV_DDR_TEMP_NORMAL, /* temperature */
  257. MV_DDR_TIM_2T} }, /* timing */
  258. BUS_MASK_32BIT, /* Busses mask */
  259. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  260. { {0} }, /* raw spd data */
  261. {0} /* timing parameters */
  262. };
  263. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  264. {
  265. if (omnia_get_ram_size_gb() == 2)
  266. return &board_topology_map_2g;
  267. else
  268. return &board_topology_map_1g;
  269. }
  270. #ifndef CONFIG_SPL_BUILD
  271. static int set_regdomain(void)
  272. {
  273. struct omnia_eeprom oep;
  274. char rd[3] = {' ', ' ', 0};
  275. if (omnia_read_eeprom(&oep))
  276. memcpy(rd, &oep.region, 2);
  277. else
  278. puts("EEPROM regdomain read failed.\n");
  279. printf("Regdomain set to %s\n", rd);
  280. return env_set("regdomain", rd);
  281. }
  282. /*
  283. * default factory reset bootcommand on Omnia first sets all the front LEDs
  284. * to green and then tries to load the rescue image from SPI flash memory and
  285. * boot it
  286. */
  287. #define OMNIA_FACTORY_RESET_BOOTCMD \
  288. "i2c dev 2; " \
  289. "i2c mw 0x2a.1 0x3 0x1c 1; " \
  290. "i2c mw 0x2a.1 0x4 0x1c 1; " \
  291. "mw.l 0x01000000 0x00ff000c; " \
  292. "i2c write 0x01000000 0x2a.1 0x5 4 -s; " \
  293. "setenv bootargs \"earlyprintk console=ttyS0,115200" \
  294. " omniarescue=$omnia_reset\"; " \
  295. "sf probe; " \
  296. "sf read 0x1000000 0x100000 0x700000; " \
  297. "bootm 0x1000000; " \
  298. "bootz 0x1000000"
  299. static void handle_reset_button(void)
  300. {
  301. int ret;
  302. u8 reset_status;
  303. ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
  304. if (ret) {
  305. printf("omnia_mcu_read failed: %i, reset status unknown!\n",
  306. ret);
  307. return;
  308. }
  309. env_set_ulong("omnia_reset", reset_status);
  310. if (reset_status) {
  311. printf("RESET button was pressed, overwriting bootcmd!\n");
  312. env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD);
  313. }
  314. }
  315. #endif
  316. int board_early_init_f(void)
  317. {
  318. /* Configure MPP */
  319. writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  320. writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  321. writel(0x11244011, MVEBU_MPP_BASE + 0x08);
  322. writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
  323. writel(0x22200002, MVEBU_MPP_BASE + 0x10);
  324. writel(0x30042022, MVEBU_MPP_BASE + 0x14);
  325. writel(0x55550555, MVEBU_MPP_BASE + 0x18);
  326. writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
  327. /* Set GPP Out value */
  328. writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  329. writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  330. /* Set GPP Polarity */
  331. writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  332. writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  333. /* Set GPP Out Enable */
  334. writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  335. writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  336. return 0;
  337. }
  338. int board_init(void)
  339. {
  340. /* address of boot parameters */
  341. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  342. #ifndef CONFIG_SPL_BUILD
  343. disable_mcu_watchdog();
  344. #endif
  345. return 0;
  346. }
  347. int board_late_init(void)
  348. {
  349. #ifndef CONFIG_SPL_BUILD
  350. set_regdomain();
  351. handle_reset_button();
  352. #endif
  353. pci_init();
  354. return 0;
  355. }
  356. static struct udevice *get_atsha204a_dev(void)
  357. {
  358. static struct udevice *dev;
  359. if (dev)
  360. return dev;
  361. if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
  362. puts("Cannot find ATSHA204A on I2C bus!\n");
  363. dev = NULL;
  364. }
  365. return dev;
  366. }
  367. int checkboard(void)
  368. {
  369. u32 version_num, serial_num;
  370. int err = 1;
  371. struct udevice *dev = get_atsha204a_dev();
  372. if (dev) {
  373. err = atsha204a_wakeup(dev);
  374. if (err)
  375. goto out;
  376. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  377. OMNIA_ATSHA204_OTP_VERSION,
  378. (u8 *)&version_num);
  379. if (err)
  380. goto out;
  381. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  382. OMNIA_ATSHA204_OTP_SERIAL,
  383. (u8 *)&serial_num);
  384. if (err)
  385. goto out;
  386. atsha204a_sleep(dev);
  387. }
  388. out:
  389. printf("Turris Omnia:\n");
  390. printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
  391. if (err)
  392. printf(" Serial Number: unknown\n");
  393. else
  394. printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num),
  395. be32_to_cpu(serial_num));
  396. return 0;
  397. }
  398. static void increment_mac(u8 *mac)
  399. {
  400. int i;
  401. for (i = 5; i >= 3; i--) {
  402. mac[i] += 1;
  403. if (mac[i])
  404. break;
  405. }
  406. }
  407. int misc_init_r(void)
  408. {
  409. int err;
  410. struct udevice *dev = get_atsha204a_dev();
  411. u8 mac0[4], mac1[4], mac[6];
  412. if (!dev)
  413. goto out;
  414. err = atsha204a_wakeup(dev);
  415. if (err)
  416. goto out;
  417. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  418. OMNIA_ATSHA204_OTP_MAC0, mac0);
  419. if (err)
  420. goto out;
  421. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  422. OMNIA_ATSHA204_OTP_MAC1, mac1);
  423. if (err)
  424. goto out;
  425. atsha204a_sleep(dev);
  426. mac[0] = mac0[1];
  427. mac[1] = mac0[2];
  428. mac[2] = mac0[3];
  429. mac[3] = mac1[1];
  430. mac[4] = mac1[2];
  431. mac[5] = mac1[3];
  432. if (is_valid_ethaddr(mac))
  433. eth_env_set_enetaddr("eth1addr", mac);
  434. increment_mac(mac);
  435. if (is_valid_ethaddr(mac))
  436. eth_env_set_enetaddr("eth2addr", mac);
  437. increment_mac(mac);
  438. if (is_valid_ethaddr(mac))
  439. eth_env_set_enetaddr("ethaddr", mac);
  440. out:
  441. return 0;
  442. }