mux.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * mux.c
  4. *
  5. * Pinmux Setting for B&R BRPPT1 Board(s)
  6. *
  7. * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
  8. * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
  9. */
  10. #include <common.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/arch/hardware.h>
  13. #include <asm/arch/mux.h>
  14. #include <asm/io.h>
  15. #include <i2c.h>
  16. static struct module_pin_mux uart0_pin_mux[] = {
  17. /* UART0_RTS */
  18. {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
  19. /* UART0_CTS */
  20. {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  21. /* UART0_RXD */
  22. {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  23. /* UART0_TXD */
  24. {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
  25. {-1},
  26. };
  27. static struct module_pin_mux uart1_pin_mux[] = {
  28. /* UART1_RTS as I2C2-SCL */
  29. {OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  30. /* UART1_CTS as I2C2-SDA */
  31. {OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  32. /* UART1_RXD */
  33. {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  34. /* UART1_TXD */
  35. {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
  36. {-1},
  37. };
  38. #ifdef CONFIG_MMC
  39. static struct module_pin_mux mmc1_pin_mux[] = {
  40. {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
  41. {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
  42. {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
  43. {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
  44. {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
  45. {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
  46. {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
  47. {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
  48. {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
  49. {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
  50. {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
  51. {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
  52. {-1},
  53. };
  54. #endif
  55. static struct module_pin_mux i2c0_pin_mux[] = {
  56. /* I2C_DATA */
  57. {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  58. /* I2C_SCLK */
  59. {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  60. {-1},
  61. };
  62. static struct module_pin_mux spi0_pin_mux[] = {
  63. /* SPI0_SCLK */
  64. {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
  65. /* SPI0_D0 */
  66. {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
  67. /* SPI0_D1 */
  68. {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
  69. /* SPI0_CS0 */
  70. {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
  71. {-1},
  72. };
  73. static struct module_pin_mux mii1_pin_mux[] = {
  74. {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
  75. {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
  76. {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
  77. {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
  78. {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
  79. {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
  80. {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
  81. {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
  82. {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
  83. {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
  84. {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
  85. {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
  86. {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
  87. {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
  88. {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
  89. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
  90. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  91. {-1},
  92. };
  93. static struct module_pin_mux mii2_pin_mux[] = {
  94. {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */
  95. {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */
  96. {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */
  97. {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */
  98. {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */
  99. {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */
  100. {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */
  101. {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */
  102. {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */
  103. {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */
  104. {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */
  105. {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */
  106. {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
  107. {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
  108. /*
  109. * MII2_CRS is shared with
  110. * NAND_WAIT0
  111. */
  112. {OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
  113. {-1},
  114. };
  115. #ifdef CONFIG_MTD_RAW_NAND
  116. static struct module_pin_mux nand_pin_mux[] = {
  117. {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
  118. {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
  119. {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
  120. {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
  121. {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
  122. {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
  123. {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
  124. {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
  125. {OFFSET(gpmc_clk), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
  126. {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
  127. {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
  128. {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
  129. {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
  130. {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
  131. {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
  132. {-1},
  133. };
  134. #endif
  135. static struct module_pin_mux gpIOs[] = {
  136. /* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
  137. {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  138. /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */
  139. {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
  140. /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */
  141. {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)},
  142. /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
  143. {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
  144. /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
  145. {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
  146. /* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
  147. {OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  148. /* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
  149. {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  150. /* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
  151. {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  152. /* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
  153. {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  154. /* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
  155. {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  156. /* GPIO2_0 (GPMC_nCS3) - DCOK */
  157. {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
  158. /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
  159. {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
  160. /*
  161. * GPIO0_7 (PWW0 OUT)
  162. * DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
  163. */
  164. {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
  165. /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
  166. {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  167. /* GPIO0_20 (DMA_INTR1) - REP-Switch */
  168. {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
  169. /* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
  170. {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
  171. /* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
  172. {OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
  173. /* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
  174. {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) },
  175. /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
  176. {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
  177. #ifndef CONFIG_MTD_RAW_NAND
  178. /* GPIO2_3 - NAND_OE */
  179. {OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
  180. /* GPIO2_4 - NAND_WEN */
  181. {OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
  182. /* GPIO2_5 - NAND_BE_CLE */
  183. {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
  184. #endif
  185. {-1},
  186. };
  187. static struct module_pin_mux lcd_pin_mux[] = {
  188. {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
  189. {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
  190. {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
  191. {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
  192. {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
  193. {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
  194. {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
  195. {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
  196. {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
  197. {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
  198. {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
  199. {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
  200. {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
  201. {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
  202. {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
  203. {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
  204. {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
  205. {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
  206. {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
  207. {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
  208. {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
  209. {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
  210. {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
  211. {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
  212. {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
  213. {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
  214. {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
  215. {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
  216. {-1},
  217. };
  218. void enable_uart0_pin_mux(void)
  219. {
  220. configure_module_pin_mux(uart0_pin_mux);
  221. }
  222. void enable_i2c_pin_mux(void)
  223. {
  224. configure_module_pin_mux(i2c0_pin_mux);
  225. }
  226. void enable_board_pin_mux(void)
  227. {
  228. configure_module_pin_mux(i2c0_pin_mux);
  229. configure_module_pin_mux(mii1_pin_mux);
  230. configure_module_pin_mux(mii2_pin_mux);
  231. #ifdef CONFIG_MTD_RAW_NAND
  232. configure_module_pin_mux(nand_pin_mux);
  233. #elif defined(CONFIG_MMC)
  234. configure_module_pin_mux(mmc1_pin_mux);
  235. #endif
  236. configure_module_pin_mux(spi0_pin_mux);
  237. configure_module_pin_mux(lcd_pin_mux);
  238. configure_module_pin_mux(uart1_pin_mux);
  239. configure_module_pin_mux(gpIOs);
  240. }