serial_starfive.c 6.1 KB

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  1. /*
  2. * Copyright (C) 2020 StarFive
  3. *
  4. * Modified to support VIC7100 SoC by StarFive
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. /* Driver Model for Serial is not defined */
  10. //#include <dm.h>
  11. #include <errno.h>
  12. #include <watchdog.h>
  13. #include <serial.h>
  14. #include <linux/compiler.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/global_reg.h>
  17. #include <asm/arch/ezGPIO_fullMux_ctrl_macro.h>
  18. #include <asm/arch/clkgen_ctrl_macro.h>
  19. #include <asm/arch/rstgen_ctrl_macro.h>
  20. #include <asm/arch/vic_module_reset_clkgen.h>
  21. /* we don't need these, just backup */
  22. #if 0
  23. #define __io_bw() __asm__ __volatile__("fence w,o" : : : "memory");
  24. #define __io_aw() do {} while (0)
  25. /* Information about a serial port */
  26. struct hive_serial_platdata {
  27. uint32_t base_addr;
  28. };
  29. /* HiFive unleashed UART register footprint */
  30. typedef struct starfive_uart {
  31. u32 txdata;
  32. u32 rxdata;
  33. u32 txctrl;
  34. u32 rxctrl;
  35. u32 ie;
  36. u32 ip;
  37. u32 div;
  38. } starfive_uart_t;
  39. #endif
  40. DECLARE_GLOBAL_DATA_PTR;
  41. /* TXCTRL register */
  42. #define UART_TXEN 0x1
  43. #define UART_TXWM(x) (((x) & 0xffff) << 16)
  44. /* RXCTRL register */
  45. #define UART_RXEN 0x1
  46. #define UART_RXWM(x) (((x) & 0xffff) << 16)
  47. /* IP register */
  48. #define UART_IP_TXWM 0x1
  49. #define UART_IP_RXWM 0x2
  50. #define UART_TXFIFO_FULL 0x80000000
  51. #define UART_RXFIFO_EMPTY 0x80000000
  52. #define SER_RBR (0x00)
  53. #define SER_THR (0x00)
  54. #define SER_DLL (0x00)
  55. #define SER_DLH (0x04)
  56. #define SER_IER (0x04)
  57. #define SER_IIR (0x08)
  58. #define SER_FCR (0x08)
  59. #define SER_LCR (0x0C)
  60. #define SER_MCR (0x10)
  61. #define SER_LSR (0x14)
  62. #define SER_MSR (0x18)
  63. #define SER_SCR (0x1C)
  64. //UART_LCR bit define
  65. #define LCR_WORD_LEN5 (0<<0)
  66. #define LCR_WORD_LEN6 (1<<0)
  67. #define LCR_WORD_LEN7 (2<<0)
  68. #define LCR_WORD_LEN8 (3<<0)
  69. #define LCR_STOP_1BIT (0<<2)
  70. #define LCR_STOP_2BIT (1<<2)
  71. #define LCR_PE (1<<3)
  72. #define LCR_EPS (1<<4)
  73. #define LCR_SP (1<<5)
  74. #define LCR_BC (1<<6)
  75. #define LCR_DLAB (1<<7)
  76. //IER, interrupt enable reg
  77. #define IER_ERBFI (1<<0) //rx interrupt enable
  78. #define IER_ETBEI (1<<1) //tx interrupt enable
  79. #define IER_ELSI (1<<2)
  80. #define IER_EDSSI (1<<3)
  81. #define IER_PTIME (1<<7)
  82. //IIR, interrupt identify reg
  83. #define INTR_ID_RLSI 0x06
  84. #define INTR_ID_DATAVL 0x04
  85. #define INTR_ID_TIMEOUT 0x0C
  86. #define INTR_ID_THR 0x02
  87. //FCR
  88. #define RCVR_TRIG_1C (0x00 << 0x06) //1 char
  89. #define RCVR_TRIG_QFL (0x01 << 0x06) //1/4 FIFO
  90. #define RCVR_TRIG_HFL (0x02 << 0x06) //1/2 FIFO
  91. #define RCVR_TRIG_LTF (0x03 << 0x06) //2 less than full
  92. #define TXEM_TRIG_EMT (0x00 << 0x04) //FIFO empty
  93. #define TXEM_TRIG_2C (0x00 << 0x04) //2 char
  94. #define TXEM_TRIG_QFL (0x02 << 0x04) //1/4 FIFO
  95. #define TXEM_TRIG_HFL (0x03 << 0x04) //1/2 FIFO
  96. #define DMA_MOD1 (0x01 << 0x03)
  97. #define DMA_MOD0 (0x00 << 0x03)
  98. #define TXFIFO_RST (0x01 << 0x02)
  99. #define RXFIFO_RST (0x01 << 0x01)
  100. #define FIFO_ENA (0x01 << 0x00)
  101. //LSR
  102. #define DATA_RDY (0x01<<0x00) //at least one byte available
  103. #define RCV_OVERUN (0x01<<0x01)
  104. #define ERR_PARITY (0x01<<0x02)
  105. #define ERR_FRAMING (0x01<<0x03)
  106. #define ID_BREAK (0x01<<0x04) //break interrupt bit
  107. #define ID_THRE (0x01<<0x05) //in FIFO THRE mode, it is the xmit fifo full flag !!!
  108. #define ID_TEMPT (0x01<<0x06)
  109. #define ERR_RPE (0x01<<0x07)
  110. /* MCR */
  111. #define MCR_DTR (0x01<<0x00) /* dtr output */
  112. #define MCR_RTS (0x01<<0x01) /* rts output */
  113. #define MCR_OUT1 (0x01<<0x02) /* output #1 */
  114. #define MCR_OUT2 (0x01<<0x03) /* output #2 */
  115. #define MCR_LOOP (0x01<<0x04) /* loop back */
  116. #define MCR_AFCE (0x01<<0x05) /* auto flow control enable */
  117. //#define DW_UART_BASE_ADDR SIFIVE_UART_BASE_ADDR
  118. static u32 starfive_uart_read(u32 reg)
  119. {
  120. return readl(SIFIVE_UART_BASE_ADDR + reg);
  121. }
  122. static void starfive_uart_write(u32 ch,u32 reg)
  123. {
  124. writel(ch,SIFIVE_UART_BASE_ADDR + reg);
  125. }
  126. static void starfive_uart_putc(const char ch)
  127. {
  128. while (!(starfive_uart_read(SER_LSR)&ID_TEMPT)) {
  129. };
  130. starfive_uart_write(ch,SER_THR);
  131. }
  132. static void starfive_uart_puts(const char *s)
  133. {
  134. while (*s){
  135. starfive_uart_putc(*s++);
  136. }
  137. }
  138. static int starfive_uart_getc(void)
  139. {
  140. /* Wait here until the the FIFO is not full */
  141. while (!(starfive_uart_read(SER_LSR) & DATA_RDY)) {
  142. };
  143. return starfive_uart_read(SER_RBR);
  144. }
  145. static void starfive_uart_setbrg(void)
  146. {
  147. u64 baud_value;
  148. /*
  149. * BAUD_VALUE = (CLOCK / BAUD_RATE) - 1
  150. */
  151. baud_value = ((SIFIVE_PERIPH_CLK_FREQ / CONFIG_BAUDRATE)>>4);
  152. starfive_uart_write(((baud_value>>0)&0xFF),SER_DLL);
  153. starfive_uart_write(((baud_value>>8)&0xFF),SER_DLH);
  154. }
  155. static void ser_clrrxtmo(void)
  156. {
  157. u32 reg32_val;
  158. while(1) {
  159. reg32_val = starfive_uart_read(SER_IIR);
  160. if((reg32_val&0xC)!=0xC)
  161. break;
  162. reg32_val=starfive_uart_read(SER_RBR);
  163. }
  164. }
  165. static int starfive_uart_init(void)
  166. {
  167. u32 datab, stopb, par, mcr;
  168. u8 databits = 8;
  169. u8 stopbits = 1;
  170. u8 parity = 0;
  171. u8 flow_ctl = 0;
  172. vic_uart0_reset_clk_gpio_evb_enable;
  173. vic_uart1_reset_clk_gpio_evb_enable;
  174. //vic_uart2_reset_clk_gpio_evb_enable;
  175. //vic_uart3_reset_clk_gpio_evb_enable;
  176. if(databits >=5 && databits <=8) {
  177. datab = (databits - 5);
  178. }
  179. else {
  180. return -1;
  181. }
  182. if(stopbits == 1) {
  183. stopb = LCR_STOP_1BIT;
  184. }
  185. else if(stopbits == 2) {
  186. stopb = LCR_STOP_2BIT;
  187. }
  188. else {
  189. return -1;
  190. }
  191. par = (parity == 0) ? 0 : (parity == 1) ? LCR_PE : (LCR_PE|LCR_EPS);
  192. mcr = (flow_ctl == 0) ? 0 : MCR_RTS | MCR_AFCE;
  193. starfive_uart_write(LCR_DLAB,SER_LCR);
  194. starfive_uart_setbrg();
  195. starfive_uart_write(datab|stopb|par,SER_LCR);
  196. //enable fifo and reset fifo, 1-byte int trig!
  197. starfive_uart_write((RCVR_TRIG_1C|TXEM_TRIG_EMT|
  198. TXFIFO_RST|RXFIFO_RST|FIFO_ENA),
  199. SER_FCR);
  200. starfive_uart_write(mcr,SER_MCR);
  201. //dis the ser interrupt
  202. starfive_uart_write(0x00,SER_IER);
  203. ser_clrrxtmo();
  204. return 0;
  205. }
  206. static int starfive_uart_tstc(void)
  207. {
  208. return ((starfive_uart_read(SER_LSR)) & (1 << 0));
  209. }
  210. static struct serial_device starfive_uart_drv = {
  211. .name = "starfive_uart",
  212. .start = starfive_uart_init,
  213. .stop = NULL,
  214. .setbrg = starfive_uart_setbrg,
  215. .putc = starfive_uart_putc,
  216. .puts = starfive_uart_puts,
  217. .getc = starfive_uart_getc,
  218. .tstc = starfive_uart_tstc,
  219. };
  220. void starfive_uart_initialize(void)
  221. {
  222. serial_register(&starfive_uart_drv);
  223. }
  224. struct serial_device *default_serial_console(void)
  225. {
  226. return &starfive_uart_drv;
  227. }