vad.h 3.7 KB

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  1. #ifndef __VAD_H__
  2. #define __VAD_H__
  3. #define VAD_LEFT_MARGIN I2S_VAD_BASE_ADDR + 0x800
  4. #define VAD_RIGHT_MARGIN I2S_VAD_BASE_ADDR + 0x804
  5. #define VAD_N_LOW_CONT_FRAMES I2S_VAD_BASE_ADDR + 0x808
  6. #define VAD_N_LOW_SEEK_FRAMES I2S_VAD_BASE_ADDR + 0x80C
  7. #define VAD_N_HIGH_CONT_FRAMES I2S_VAD_BASE_ADDR + 0x810
  8. #define VAD_N_HIGH_SEEK_FRAMES I2S_VAD_BASE_ADDR + 0x814
  9. #define VAD_N_SPEECH_LOW_HIGH_FRAMES I2S_VAD_BASE_ADDR + 0x818
  10. #define VAD_N_SPEECH_LOW_SEEK_FRAMES I2S_VAD_BASE_ADDR + 0x81C
  11. #define VAD_MEAN_SIL_FRAMES I2S_VAD_BASE_ADDR + 0x820
  12. #define VAD_N_ALPHA I2S_VAD_BASE_ADDR + 0x824
  13. #define VAD_N_BETA I2S_VAD_BASE_ADDR + 0x828
  14. #define VAD_FIFO_DEPTH I2S_VAD_BASE_ADDR + 0x82C
  15. #define VAD_LR_SEL I2S_VAD_BASE_ADDR + 0x840
  16. #define VAD_SW I2S_VAD_BASE_ADDR + 0x844
  17. #define VAD_LEFT_WD I2S_VAD_BASE_ADDR + 0x848
  18. #define VAD_RIGHT_WD I2S_VAD_BASE_ADDR + 0x84C
  19. #define VAD_STOP_DELAY I2S_VAD_BASE_ADDR + 0x850
  20. #define VAD_ADDR_START I2S_VAD_BASE_ADDR + 0x854
  21. #define VAD_ADDR_WRAP I2S_VAD_BASE_ADDR + 0x858
  22. #define VAD_MEM_SW I2S_VAD_BASE_ADDR + 0x85C
  23. #define VAD_SPINT_CLR I2S_VAD_BASE_ADDR + 0x860
  24. #define VAD_SPINT_EN I2S_VAD_BASE_ADDR + 0x864
  25. #define VAD_SLINT_CLR I2S_VAD_BASE_ADDR + 0x868
  26. #define VAD_SLINT_EN I2S_VAD_BASE_ADDR + 0x86C
  27. #define VAD_RAW_SPINT I2S_VAD_BASE_ADDR + 0x870
  28. #define VAD_RAW_SLINT I2S_VAD_BASE_ADDR + 0x874
  29. #define VAD_SPINT I2S_VAD_BASE_ADDR + 0x878
  30. #define VAD_SLINT I2S_VAD_BASE_ADDR + 0x87C
  31. #define VAD_XMEM_ADDR (I2S_VAD_BASE_ADDR + 0x880) //16bit index
  32. #define SCFG_vad_i2s_ctrl_REG_ADDR (I2S_VAD_BASE_ADDR + 0x884)
  33. #define VAD_AIX_MEM_ADDR (0x701F0000)
  34. #define _SET_SYSCON_REG_SCFG_ctrl_i2sadc_enable { \
  35. uint32_t value = MA_INW(VAD_SW); \
  36. value &= ~(1<<1); \
  37. value |= (1<<1); \
  38. MA_OUTW(VAD_SW, value); \
  39. }
  40. #define _SET_SYSCON_REG_SCFG_ctrl_i2sadc_disable { \
  41. uint32_t value = MA_INW(VAD_SW); \
  42. value &= ~(1<<1); \
  43. MA_OUTW(VAD_SW, value); \
  44. }
  45. #define _SET_SYSCON_REG_SCFG_aon_i2s_ctrl_adci2s_d0_sel(v) { \
  46. uint32_t _ezchip_macro_read_value_=MA_INW(SCFG_vad_i2s_ctrl_REG_ADDR); \
  47. _ezchip_macro_read_value_ &= ~(0x7); \
  48. _ezchip_macro_read_value_ |= (v&0x7); \
  49. MA_OUTW(SCFG_vad_i2s_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  50. }
  51. #define _GET_SYSCON_REG_SCFG_aon_i2s_ctrl_adci2s_d0_sel(_ezchip_read_value_) { \
  52. uint32_t _ezchip_macro_read_value_=MA_INW(SCFG_vad_i2s_ctrl_REG_ADDR); \
  53. _ezchip_macro_read_value_ &= 0x7;\
  54. }
  55. #define _SET_SYSCON_REG_SCFG_aon_i2s_ctrl_adci2s_d1_sel(v) { \
  56. uint32_t _ezchip_macro_read_value_=MA_INW(SCFG_vad_i2s_ctrl_REG_ADDR); \
  57. _ezchip_macro_read_value_ &= ~(0x7<<3); \
  58. _ezchip_macro_read_value_ |= (v&0x7)<<3; \
  59. MA_OUTW(SCFG_vad_i2s_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  60. }
  61. #define _GET_SYSCON_REG_SCFG_aon_i2s_ctrl_adci2s_d1_sel(_ezchip_read_value_) { \
  62. uint32_t _ezchip_macro_read_value_=MA_INW(SCFG_vad_i2s_ctrl_REG_ADDR) >> 3; \
  63. _ezchip_macro_read_value_ &= 0x7;\
  64. }
  65. #define _SET_SYSCON_REG_SCFG_aon_i2s_ctrl_adci2s_d2_sel(v) { \
  66. uint32_t _ezchip_macro_read_value_=MA_INW(SCFG_vad_i2s_ctrl_REG_ADDR); \
  67. _ezchip_macro_read_value_ &= ~(0x7<<6); \
  68. _ezchip_macro_read_value_ |= (v&0x7)<<6; \
  69. MA_OUTW(SCFG_vad_i2s_ctrl_REG_ADDR,_ezchip_macro_read_value_); \
  70. }
  71. #define _GET_SYSCON_REG_SCFG_aon_i2s_ctrl_adci2s_d2_sel(_ezchip_read_value_) { \
  72. uint32_t _ezchip_macro_read_value_=MA_INW(SCFG_vad_i2s_ctrl_REG_ADDR) >> 6; \
  73. _ezchip_macro_read_value_ &= 0x7;\
  74. }
  75. #endif